mirror of https://github.com/YosysHQ/yosys.git
memory_share: Improve sat-based port sharing.
This commit is contained in:
Marcelina Kościelnicka
parent
cbf6b719fe
commit
2d10caabbc
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@ -139,13 +139,9 @@ struct MemoryShareWorker
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if (GetSize(mem.wr_ports) <= 1)
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if (GetSize(mem.wr_ports) <= 1)
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return;
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return;
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ezSatPtr ez;
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// Get a list of ports that have any chance of being mergeable.
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SatGen satgen(ez.get(), &modwalker.sigmap);
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// find list of considered ports and port pairs
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pool<int> eligible_ports;
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std::set<int> considered_ports;
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std::set<int> considered_port_pairs;
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for (int i = 0; i < GetSize(mem.wr_ports); i++) {
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for (int i = 0; i < GetSize(mem.wr_ports); i++) {
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auto &port = mem.wr_ports[i];
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auto &port = mem.wr_ports[i];
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@ -154,152 +150,190 @@ struct MemoryShareWorker
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if (bit == RTLIL::State::S1)
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if (bit == RTLIL::State::S1)
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goto port_is_always_active;
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goto port_is_always_active;
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if (modwalker.has_drivers(bits))
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if (modwalker.has_drivers(bits))
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considered_ports.insert(i);
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eligible_ports.insert(i);
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port_is_always_active:;
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port_is_always_active:;
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}
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}
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if (eligible_ports.size() <= 1)
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return;
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log("Consolidating write ports of memory %s.%s using sat-based resource sharing:\n", log_id(module), log_id(mem.memid));
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log("Consolidating write ports of memory %s.%s using sat-based resource sharing:\n", log_id(module), log_id(mem.memid));
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bool cache_clk_enable = false;
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// Group eligible ports by clock domain and width.
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bool cache_clk_polarity = false;
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RTLIL::SigSpec cache_clk;
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int cache_wide_log2 = 0;
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pool<int> checked_ports;
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std::vector<std::vector<int>> groups;
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for (int i = 0; i < GetSize(mem.wr_ports); i++)
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for (int i = 0; i < GetSize(mem.wr_ports); i++)
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{
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{
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auto &port = mem.wr_ports[i];
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auto &port1 = mem.wr_ports[i];
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if (!eligible_ports.count(i))
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continue;
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if (checked_ports.count(i))
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continue;
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if (port.clk_enable != cache_clk_enable ||
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port.wide_log2 != cache_wide_log2 ||
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std::vector<int> group;
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(cache_clk_enable && (sigmap(port.clk) != cache_clk ||
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group.push_back(i);
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port.clk_polarity != cache_clk_polarity)))
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for (int j = i + 1; j < GetSize(mem.wr_ports); j++)
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{
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{
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cache_clk_enable = port.clk_enable;
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auto &port2 = mem.wr_ports[j];
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cache_clk_polarity = port.clk_polarity;
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if (!eligible_ports.count(j))
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cache_clk = sigmap(port.clk);
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continue;
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cache_wide_log2 = port.wide_log2;
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if (checked_ports.count(j))
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continue;
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if (port1.clk_enable != port2.clk_enable)
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continue;
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if (port1.clk_enable) {
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if (port1.clk != port2.clk)
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continue;
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if (port1.clk_polarity != port2.clk_polarity)
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continue;
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}
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if (port1.wide_log2 != port2.wide_log2)
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continue;
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group.push_back(j);
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}
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}
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else if (i > 0 && considered_ports.count(i-1) && considered_ports.count(i))
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considered_port_pairs.insert(i);
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if (cache_clk_enable)
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for (auto j : group)
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log(" Port %d on %s %s: %s\n", i,
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checked_ports.insert(j);
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cache_clk_polarity ? "posedge" : "negedge", log_signal(cache_clk),
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considered_ports.count(i) ? "considered" : "not considered");
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if (group.size() <= 1)
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else
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continue;
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log(" Port %d unclocked: %s\n", i,
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considered_ports.count(i) ? "considered" : "not considered");
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groups.push_back(group);
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}
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}
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if (considered_port_pairs.size() < 1) {
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bool changed = false;
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log(" No two subsequent ports in same clock domain considered -> nothing to consolidate.\n");
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for (auto &group : groups) {
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return;
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auto &some_port = mem.wr_ports[group[0]];
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}
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string ports;
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for (auto idx : group) {
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if (idx != group[0])
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ports += ", ";
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ports += std::to_string(idx);
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}
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if (!some_port.clk_enable) {
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log(" Checking unclocked group, width %d: ports %s.\n", mem.width << some_port.wide_log2, ports.c_str());
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} else {
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log(" Checking group clocked with %sedge %s, width %d: ports %s.\n", some_port.clk_polarity ? "pos" : "neg", log_signal(some_port.clk), mem.width << some_port.wide_log2, ports.c_str());
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}
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// create SAT representation of common input cone of all considered EN signals
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// Okay, time to actually run the SAT solver.
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pool<Wire*> one_hot_wires;
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ezSatPtr ez;
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std::set<RTLIL::Cell*> sat_cells;
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SatGen satgen(ez.get(), &modwalker.sigmap);
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std::set<RTLIL::SigBit> bits_queue;
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std::map<int, int> port_to_sat_variable;
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for (int i = 0; i < GetSize(mem.wr_ports); i++)
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// create SAT representation of common input cone of all considered EN signals
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if (considered_port_pairs.count(i) || considered_port_pairs.count(i+1))
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{
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pool<Wire*> one_hot_wires;
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RTLIL::SigSpec sig = modwalker.sigmap(mem.wr_ports[i].en);
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std::set<RTLIL::Cell*> sat_cells;
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port_to_sat_variable[i] = ez->expression(ez->OpOr, satgen.importSigSpec(sig));
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std::set<RTLIL::SigBit> bits_queue;
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dict<int, int> port_to_sat_variable;
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for (auto idx : group) {
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RTLIL::SigSpec sig = modwalker.sigmap(mem.wr_ports[idx].en);
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port_to_sat_variable[idx] = ez->expression(ez->OpOr, satgen.importSigSpec(sig));
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std::vector<RTLIL::SigBit> bits = sig;
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std::vector<RTLIL::SigBit> bits = sig;
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bits_queue.insert(bits.begin(), bits.end());
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bits_queue.insert(bits.begin(), bits.end());
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}
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}
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while (!bits_queue.empty())
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while (!bits_queue.empty())
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{
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{
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for (auto bit : bits_queue)
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for (auto bit : bits_queue)
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if (bit.wire && bit.wire->get_bool_attribute(ID::onehot))
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if (bit.wire && bit.wire->get_bool_attribute(ID::onehot))
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one_hot_wires.insert(bit.wire);
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one_hot_wires.insert(bit.wire);
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pool<ModWalker::PortBit> portbits;
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pool<ModWalker::PortBit> portbits;
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modwalker.get_drivers(portbits, bits_queue);
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modwalker.get_drivers(portbits, bits_queue);
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bits_queue.clear();
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bits_queue.clear();
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for (auto &pbit : portbits)
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for (auto &pbit : portbits)
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if (sat_cells.count(pbit.cell) == 0 && cone_ct.cell_known(pbit.cell->type)) {
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if (sat_cells.count(pbit.cell) == 0 && cone_ct.cell_known(pbit.cell->type)) {
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pool<RTLIL::SigBit> &cell_inputs = modwalker.cell_inputs[pbit.cell];
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pool<RTLIL::SigBit> &cell_inputs = modwalker.cell_inputs[pbit.cell];
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bits_queue.insert(cell_inputs.begin(), cell_inputs.end());
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bits_queue.insert(cell_inputs.begin(), cell_inputs.end());
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sat_cells.insert(pbit.cell);
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sat_cells.insert(pbit.cell);
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}
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}
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}
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for (auto wire : one_hot_wires) {
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log(" Adding one-hot constraint for wire %s.\n", log_id(wire));
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vector<int> ez_wire_bits = satgen.importSigSpec(wire);
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for (int i : ez_wire_bits)
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for (int j : ez_wire_bits)
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if (i != j) ez->assume(ez->NOT(i), j);
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}
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log(" Common input cone for all EN signals: %d cells.\n", int(sat_cells.size()));
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for (auto cell : sat_cells)
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satgen.importCell(cell);
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log(" Size of unconstrained SAT problem: %d variables, %d clauses\n", ez->numCnfVariables(), ez->numCnfClauses());
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// merge subsequent ports if possible
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bool changed = false;
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for (int i = 0; i < GetSize(mem.wr_ports); i++)
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{
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if (!considered_port_pairs.count(i))
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continue;
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if (ez->solve(port_to_sat_variable.at(i-1), port_to_sat_variable.at(i))) {
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log(" According to SAT solver sharing of port %d with port %d is not possible.\n", i-1, i);
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continue;
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}
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}
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log(" Merging port %d into port %d.\n", i-1, i);
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for (auto wire : one_hot_wires) {
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port_to_sat_variable.at(i) = ez->OR(port_to_sat_variable.at(i-1), port_to_sat_variable.at(i));
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log(" Adding one-hot constraint for wire %s.\n", log_id(wire));
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vector<int> ez_wire_bits = satgen.importSigSpec(wire);
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RTLIL::SigSpec last_addr = mem.wr_ports[i-1].addr;
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for (int i : ez_wire_bits)
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RTLIL::SigSpec last_data = mem.wr_ports[i-1].data;
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for (int j : ez_wire_bits)
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std::vector<RTLIL::SigBit> last_en = modwalker.sigmap(mem.wr_ports[i-1].en);
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if (i != j) ez->assume(ez->NOT(i), j);
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RTLIL::SigSpec this_addr = mem.wr_ports[i].addr;
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RTLIL::SigSpec this_data = mem.wr_ports[i].data;
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std::vector<RTLIL::SigBit> this_en = modwalker.sigmap(mem.wr_ports[i].en);
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RTLIL::SigBit this_en_active = module->ReduceOr(NEW_ID, this_en);
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if (GetSize(last_addr) < GetSize(this_addr))
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last_addr.extend_u0(GetSize(this_addr));
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else
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this_addr.extend_u0(GetSize(last_addr));
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mem.wr_ports[i].addr = module->Mux(NEW_ID, last_addr, this_addr, this_en_active);
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mem.wr_ports[i].data = module->Mux(NEW_ID, last_data, this_data, this_en_active);
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std::map<std::pair<RTLIL::SigBit, RTLIL::SigBit>, int> groups_en;
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RTLIL::SigSpec grouped_last_en, grouped_this_en, en;
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RTLIL::Wire *grouped_en = module->addWire(NEW_ID, 0);
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for (int j = 0; j < int(this_en.size()); j++) {
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std::pair<RTLIL::SigBit, RTLIL::SigBit> key(last_en[j], this_en[j]);
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if (!groups_en.count(key)) {
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grouped_last_en.append(last_en[j]);
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grouped_this_en.append(this_en[j]);
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groups_en[key] = grouped_en->width;
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grouped_en->width++;
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}
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en.append(RTLIL::SigSpec(grouped_en, groups_en[key]));
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}
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}
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module->addMux(NEW_ID, grouped_last_en, grouped_this_en, this_en_active, grouped_en);
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log(" Common input cone for all EN signals: %d cells.\n", int(sat_cells.size()));
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mem.wr_ports[i].en = en;
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mem.wr_ports[i-1].removed = true;
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for (auto cell : sat_cells)
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changed = true;
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satgen.importCell(cell);
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log(" Size of unconstrained SAT problem: %d variables, %d clauses\n", ez->numCnfVariables(), ez->numCnfClauses());
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// now try merging the ports.
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for (int ii = 0; ii < GetSize(group); ii++) {
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int idx1 = group[ii];
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auto &port1 = mem.wr_ports[idx1];
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if (port1.removed)
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continue;
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for (int jj = ii + 1; jj < GetSize(group); jj++) {
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int idx2 = group[jj];
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auto &port2 = mem.wr_ports[idx2];
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if (port2.removed)
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continue;
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if (ez->solve(port_to_sat_variable.at(idx1), port_to_sat_variable.at(idx2))) {
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log(" According to SAT solver sharing of port %d with port %d is not possible.\n", idx1, idx2);
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continue;
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}
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log(" Merging port %d into port %d.\n", idx2, idx1);
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mem.prepare_wr_merge(idx1, idx2);
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port_to_sat_variable.at(idx1) = ez->OR(port_to_sat_variable.at(idx1), port_to_sat_variable.at(idx2));
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RTLIL::SigSpec last_addr = port1.addr;
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RTLIL::SigSpec last_data = port1.data;
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std::vector<RTLIL::SigBit> last_en = modwalker.sigmap(port1.en);
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RTLIL::SigSpec this_addr = port2.addr;
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RTLIL::SigSpec this_data = port2.data;
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std::vector<RTLIL::SigBit> this_en = modwalker.sigmap(port2.en);
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RTLIL::SigBit this_en_active = module->ReduceOr(NEW_ID, this_en);
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if (GetSize(last_addr) < GetSize(this_addr))
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last_addr.extend_u0(GetSize(this_addr));
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else
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this_addr.extend_u0(GetSize(last_addr));
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port1.addr = module->Mux(NEW_ID, last_addr, this_addr, this_en_active);
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port1.data = module->Mux(NEW_ID, last_data, this_data, this_en_active);
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std::map<std::pair<RTLIL::SigBit, RTLIL::SigBit>, int> groups_en;
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RTLIL::SigSpec grouped_last_en, grouped_this_en, en;
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RTLIL::Wire *grouped_en = module->addWire(NEW_ID, 0);
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for (int j = 0; j < int(this_en.size()); j++) {
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std::pair<RTLIL::SigBit, RTLIL::SigBit> key(last_en[j], this_en[j]);
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if (!groups_en.count(key)) {
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grouped_last_en.append(last_en[j]);
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grouped_this_en.append(this_en[j]);
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groups_en[key] = grouped_en->width;
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grouped_en->width++;
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}
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en.append(RTLIL::SigSpec(grouped_en, groups_en[key]));
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}
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module->addMux(NEW_ID, grouped_last_en, grouped_this_en, this_en_active, grouped_en);
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port1.en = en;
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port2.removed = true;
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changed = true;
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}
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}
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}
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}
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if (changed)
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if (changed)
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