mirror of https://github.com/YosysHQ/yosys.git
434 lines
13 KiB
C++
434 lines
13 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/satgen.h"
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#include "kernel/sigtools.h"
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#include "kernel/modtools.h"
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#include "kernel/mem.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct MemoryShareWorker
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{
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RTLIL::Design *design;
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RTLIL::Module *module;
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SigMap sigmap, sigmap_xmux;
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ModWalker modwalker;
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CellTypes cone_ct;
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bool flag_widen;
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// ------------------------------------------------------
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// Consolidate write ports that write to the same address
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// (or close enough to be merged to wide ports)
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// ------------------------------------------------------
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bool consolidate_wr_by_addr(Mem &mem)
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{
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if (GetSize(mem.wr_ports) <= 1)
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return false;
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log("Consolidating write ports of memory %s.%s by address:\n", log_id(module), log_id(mem.memid));
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bool changed = false;
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for (int i = 0; i < GetSize(mem.wr_ports); i++)
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{
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auto &port1 = mem.wr_ports[i];
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if (port1.removed)
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continue;
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if (!port1.clk_enable)
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continue;
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for (int j = i + 1; j < GetSize(mem.wr_ports); j++)
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{
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auto &port2 = mem.wr_ports[j];
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if (port2.removed)
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continue;
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if (!port2.clk_enable)
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continue;
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if (port1.clk != port2.clk)
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continue;
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if (port1.clk_polarity != port2.clk_polarity)
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continue;
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// If the width of the ports doesn't match, they can still be
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// merged by widening the narrow one. Check if the conditions
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// hold for that.
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int wide_log2 = std::max(port1.wide_log2, port2.wide_log2);
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if (GetSize(port1.addr) <= wide_log2)
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continue;
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if (GetSize(port2.addr) <= wide_log2)
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continue;
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if (!port1.addr.extract(0, wide_log2).is_fully_const())
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continue;
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if (!port2.addr.extract(0, wide_log2).is_fully_const())
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continue;
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if (sigmap_xmux(port1.addr.extract_end(wide_log2)) != sigmap_xmux(port2.addr.extract_end(wide_log2))) {
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// Incompatible addresses after widening. Last chance — widen both
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// ports by one more bit to merge them.
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if (!flag_widen)
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continue;
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wide_log2++;
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if (sigmap_xmux(port1.addr.extract_end(wide_log2)) != sigmap_xmux(port2.addr.extract_end(wide_log2)))
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continue;
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if (!port1.addr.extract(0, wide_log2).is_fully_const())
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continue;
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if (!port2.addr.extract(0, wide_log2).is_fully_const())
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continue;
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}
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log(" Merging ports %d, %d (address %s).\n", i, j, log_signal(port1.addr));
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mem.prepare_wr_merge(i, j);
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port1.addr = sigmap_xmux(port1.addr);
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port2.addr = sigmap_xmux(port2.addr);
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mem.widen_wr_port(i, wide_log2);
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mem.widen_wr_port(j, wide_log2);
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int pos = 0;
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while (pos < GetSize(port1.data)) {
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int epos = pos;
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while (epos < GetSize(port1.data) && port1.en[epos] == port1.en[pos] && port2.en[epos] == port2.en[pos])
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epos++;
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int width = epos - pos;
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SigBit new_en;
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if (port2.en[pos] == State::S0) {
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new_en = port1.en[pos];
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} else if (port1.en[pos] == State::S0) {
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port1.data.replace(pos, port2.data.extract(pos, width));
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new_en = port2.en[pos];
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} else {
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port1.data.replace(pos, module->Mux(NEW_ID, port1.data.extract(pos, width), port2.data.extract(pos, width), port2.en[pos]));
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new_en = module->Or(NEW_ID, port1.en[pos], port2.en[pos]);
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}
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for (int k = pos; k < epos; k++)
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port1.en[k] = new_en;
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pos = epos;
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}
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changed = true;
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port2.removed = true;
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}
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}
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if (changed)
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mem.emit();
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return changed;
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}
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// --------------------------------------------------------
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// Consolidate write ports using sat-based resource sharing
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// --------------------------------------------------------
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void consolidate_wr_using_sat(Mem &mem)
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{
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if (GetSize(mem.wr_ports) <= 1)
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return;
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// Get a list of ports that have any chance of being mergeable.
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pool<int> eligible_ports;
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for (int i = 0; i < GetSize(mem.wr_ports); i++) {
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auto &port = mem.wr_ports[i];
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std::vector<RTLIL::SigBit> bits = modwalker.sigmap(port.en);
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for (auto bit : bits)
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if (bit == RTLIL::State::S1)
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goto port_is_always_active;
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if (modwalker.has_drivers(bits))
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eligible_ports.insert(i);
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port_is_always_active:;
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}
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if (eligible_ports.size() <= 1)
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return;
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log("Consolidating write ports of memory %s.%s using sat-based resource sharing:\n", log_id(module), log_id(mem.memid));
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// Group eligible ports by clock domain and width.
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pool<int> checked_ports;
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std::vector<std::vector<int>> groups;
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for (int i = 0; i < GetSize(mem.wr_ports); i++)
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{
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auto &port1 = mem.wr_ports[i];
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if (!eligible_ports.count(i))
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continue;
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if (checked_ports.count(i))
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continue;
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std::vector<int> group;
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group.push_back(i);
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for (int j = i + 1; j < GetSize(mem.wr_ports); j++)
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{
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auto &port2 = mem.wr_ports[j];
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if (!eligible_ports.count(j))
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continue;
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if (checked_ports.count(j))
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continue;
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if (port1.clk_enable != port2.clk_enable)
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continue;
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if (port1.clk_enable) {
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if (port1.clk != port2.clk)
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continue;
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if (port1.clk_polarity != port2.clk_polarity)
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continue;
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}
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if (port1.wide_log2 != port2.wide_log2)
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continue;
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group.push_back(j);
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}
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for (auto j : group)
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checked_ports.insert(j);
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if (group.size() <= 1)
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continue;
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groups.push_back(group);
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}
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bool changed = false;
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for (auto &group : groups) {
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auto &some_port = mem.wr_ports[group[0]];
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string ports;
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for (auto idx : group) {
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if (idx != group[0])
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ports += ", ";
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ports += std::to_string(idx);
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}
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if (!some_port.clk_enable) {
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log(" Checking unclocked group, width %d: ports %s.\n", mem.width << some_port.wide_log2, ports.c_str());
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} else {
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log(" Checking group clocked with %sedge %s, width %d: ports %s.\n", some_port.clk_polarity ? "pos" : "neg", log_signal(some_port.clk), mem.width << some_port.wide_log2, ports.c_str());
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}
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// Okay, time to actually run the SAT solver.
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ezSatPtr ez;
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SatGen satgen(ez.get(), &modwalker.sigmap);
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// create SAT representation of common input cone of all considered EN signals
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pool<Wire*> one_hot_wires;
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std::set<RTLIL::Cell*> sat_cells;
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std::set<RTLIL::SigBit> bits_queue;
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dict<int, int> port_to_sat_variable;
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for (auto idx : group) {
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RTLIL::SigSpec sig = modwalker.sigmap(mem.wr_ports[idx].en);
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port_to_sat_variable[idx] = ez->expression(ez->OpOr, satgen.importSigSpec(sig));
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std::vector<RTLIL::SigBit> bits = sig;
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bits_queue.insert(bits.begin(), bits.end());
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}
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while (!bits_queue.empty())
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{
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for (auto bit : bits_queue)
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if (bit.wire && bit.wire->get_bool_attribute(ID::onehot))
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one_hot_wires.insert(bit.wire);
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pool<ModWalker::PortBit> portbits;
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modwalker.get_drivers(portbits, bits_queue);
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bits_queue.clear();
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for (auto &pbit : portbits)
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if (sat_cells.count(pbit.cell) == 0 && cone_ct.cell_known(pbit.cell->type)) {
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pool<RTLIL::SigBit> &cell_inputs = modwalker.cell_inputs[pbit.cell];
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bits_queue.insert(cell_inputs.begin(), cell_inputs.end());
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sat_cells.insert(pbit.cell);
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}
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}
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for (auto wire : one_hot_wires) {
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log(" Adding one-hot constraint for wire %s.\n", log_id(wire));
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vector<int> ez_wire_bits = satgen.importSigSpec(wire);
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for (int i : ez_wire_bits)
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for (int j : ez_wire_bits)
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if (i != j) ez->assume(ez->NOT(i), j);
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}
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log(" Common input cone for all EN signals: %d cells.\n", int(sat_cells.size()));
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for (auto cell : sat_cells)
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satgen.importCell(cell);
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log(" Size of unconstrained SAT problem: %d variables, %d clauses\n", ez->numCnfVariables(), ez->numCnfClauses());
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// now try merging the ports.
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for (int ii = 0; ii < GetSize(group); ii++) {
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int idx1 = group[ii];
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auto &port1 = mem.wr_ports[idx1];
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if (port1.removed)
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continue;
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for (int jj = ii + 1; jj < GetSize(group); jj++) {
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int idx2 = group[jj];
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auto &port2 = mem.wr_ports[idx2];
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if (port2.removed)
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continue;
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if (ez->solve(port_to_sat_variable.at(idx1), port_to_sat_variable.at(idx2))) {
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log(" According to SAT solver sharing of port %d with port %d is not possible.\n", idx1, idx2);
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continue;
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}
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log(" Merging port %d into port %d.\n", idx2, idx1);
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mem.prepare_wr_merge(idx1, idx2);
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port_to_sat_variable.at(idx1) = ez->OR(port_to_sat_variable.at(idx1), port_to_sat_variable.at(idx2));
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RTLIL::SigSpec last_addr = port1.addr;
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RTLIL::SigSpec last_data = port1.data;
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std::vector<RTLIL::SigBit> last_en = modwalker.sigmap(port1.en);
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RTLIL::SigSpec this_addr = port2.addr;
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RTLIL::SigSpec this_data = port2.data;
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std::vector<RTLIL::SigBit> this_en = modwalker.sigmap(port2.en);
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RTLIL::SigBit this_en_active = module->ReduceOr(NEW_ID, this_en);
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if (GetSize(last_addr) < GetSize(this_addr))
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last_addr.extend_u0(GetSize(this_addr));
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else
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this_addr.extend_u0(GetSize(last_addr));
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port1.addr = module->Mux(NEW_ID, last_addr, this_addr, this_en_active);
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port1.data = module->Mux(NEW_ID, last_data, this_data, this_en_active);
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std::map<std::pair<RTLIL::SigBit, RTLIL::SigBit>, int> groups_en;
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RTLIL::SigSpec grouped_last_en, grouped_this_en, en;
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RTLIL::Wire *grouped_en = module->addWire(NEW_ID, 0);
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for (int j = 0; j < int(this_en.size()); j++) {
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std::pair<RTLIL::SigBit, RTLIL::SigBit> key(last_en[j], this_en[j]);
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if (!groups_en.count(key)) {
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grouped_last_en.append(last_en[j]);
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grouped_this_en.append(this_en[j]);
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groups_en[key] = grouped_en->width;
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grouped_en->width++;
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}
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en.append(RTLIL::SigSpec(grouped_en, groups_en[key]));
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}
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module->addMux(NEW_ID, grouped_last_en, grouped_this_en, this_en_active, grouped_en);
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port1.en = en;
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port2.removed = true;
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changed = true;
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}
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}
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}
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if (changed)
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mem.emit();
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}
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// -------------
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// Setup and run
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// -------------
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MemoryShareWorker(RTLIL::Design *design, bool flag_widen) : design(design), modwalker(design), flag_widen(flag_widen) {}
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void operator()(RTLIL::Module* module)
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{
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std::vector<Mem> memories = Mem::get_selected_memories(module);
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this->module = module;
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sigmap.set(module);
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sigmap_xmux = sigmap;
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for (auto cell : module->cells())
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{
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if (cell->type == ID($mux))
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{
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RTLIL::SigSpec sig_a = sigmap_xmux(cell->getPort(ID::A));
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RTLIL::SigSpec sig_b = sigmap_xmux(cell->getPort(ID::B));
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if (sig_a.is_fully_undef())
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sigmap_xmux.add(cell->getPort(ID::Y), sig_b);
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else if (sig_b.is_fully_undef())
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sigmap_xmux.add(cell->getPort(ID::Y), sig_a);
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}
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}
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for (auto &mem : memories) {
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while (consolidate_wr_by_addr(mem));
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}
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cone_ct.setup_internals();
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cone_ct.cell_types.erase(ID($mul));
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cone_ct.cell_types.erase(ID($mod));
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cone_ct.cell_types.erase(ID($div));
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cone_ct.cell_types.erase(ID($modfloor));
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cone_ct.cell_types.erase(ID($divfloor));
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cone_ct.cell_types.erase(ID($pow));
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cone_ct.cell_types.erase(ID($shl));
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cone_ct.cell_types.erase(ID($shr));
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cone_ct.cell_types.erase(ID($sshl));
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cone_ct.cell_types.erase(ID($sshr));
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cone_ct.cell_types.erase(ID($shift));
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cone_ct.cell_types.erase(ID($shiftx));
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modwalker.setup(module, &cone_ct);
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for (auto &mem : memories)
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consolidate_wr_using_sat(mem);
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}
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};
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struct MemorySharePass : public Pass {
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MemorySharePass() : Pass("memory_share", "consolidate memory ports") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" memory_share [selection]\n");
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log("\n");
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log("This pass merges share-able memory ports into single memory ports.\n");
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log("\n");
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log("The following methods are used to consolidate the number of memory ports:\n");
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log("\n");
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log(" - When multiple write ports access the same address then this is converted\n");
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log(" to a single write port with a more complex data and/or enable logic path.\n");
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log("\n");
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log(" - When multiple write ports are never accessed at the same time (a SAT\n");
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log(" solver is used to determine this), then the ports are merged into a single\n");
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log(" write port.\n");
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log("\n");
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log("Note that in addition to the algorithms implemented in this pass, the $memrd\n");
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log("and $memwr cells are also subject to generic resource sharing passes (and other\n");
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log("optimizations) such as \"share\" and \"opt_merge\".\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override {
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log_header(design, "Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).\n");
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// TODO: expose when wide ports are actually supported.
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bool flag_widen = false;
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extra_args(args, 1, design);
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MemoryShareWorker msw(design, flag_widen);
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for (auto module : design->selected_modules())
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msw(module);
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}
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} MemorySharePass;
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PRIVATE_NAMESPACE_END
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