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Merge pull request #1 from YosysHQ/master 

merge with YosysHQ master
This commit is contained in:
Jim Lawson 2018-08-22 08:42:34 -07:00 committed by GitHub
parent 8b92ddb9d2 408077769f
commit 2c0601eb6f
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GPG Key ID: 4AEE18F83AFDEB23
196 changed files with 2530 additions and 767 deletions
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2
CodingReadme
View File

@ -21,7 +21,7 @@ Here is a the C++ code for a "hello_world" Yosys command (hello.cc):
struct HelloWorldPass : public Pass { struct HelloWorldPass : public Pass {
HelloWorldPass() : Pass("hello_world") { } HelloWorldPass() : Pass("hello_world") { }
virtual void execute(vector<string>, Design*) { void execute(vector<string>, Design*) override {
log("Hello World!\n"); log("Hello World!\n");
} }
} HelloWorldPass; } HelloWorldPass;

51
Makefile
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@ -5,6 +5,7 @@ CONFIG := clang
# CONFIG := emcc # CONFIG := emcc
# CONFIG := mxe # CONFIG := mxe
# CONFIG := msys2 # CONFIG := msys2
# CONFIG := msys2-64
# features (the more the better) # features (the more the better)
ENABLE_TCL := 1 ENABLE_TCL := 1
@ -107,7 +108,7 @@ OBJS = kernel/version_$(GIT_REV).o
# is just a symlink to your actual ABC working directory, as 'make mrproper' # is just a symlink to your actual ABC working directory, as 'make mrproper'
# will remove the 'abc' directory and you do not want to accidentally # will remove the 'abc' directory and you do not want to accidentally
# delete your work on ABC.. # delete your work on ABC..
ABCREV = 6df1396 ABCREV = ae6716b
ABCPULL = 1 ABCPULL = 1
ABCURL ?= https://github.com/berkeley-abc/abc ABCURL ?= https://github.com/berkeley-abc/abc
ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1
@ -155,6 +156,18 @@ LD = gcc
CXXFLAGS += -std=c++11 -Os CXXFLAGS += -std=c++11 -Os
ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H" ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H"
else ifeq ($(CONFIG),gcc-static)
LD = $(CXX)
LDFLAGS := $(filter-out -rdynamic,$(LDFLAGS)) -s
LDLIBS := $(filter-out -lrt,$(LDLIBS))
CXXFLAGS := $(filter-out -fPIC,$(CXXFLAGS))
CXXFLAGS += -std=c++11 -Os
ABCMKARGS = CC="$(CC)" CXX="$(CXX)" LD="$(LD)" ABC_USE_LIBSTDCXX=1 LIBS="-lm -lpthread -static" OPTFLAGS="-O" \
ARCHFLAGS="-DABC_USE_STDINT_H -DABC_NO_DYNAMIC_LINKING=1 -Wno-unused-but-set-variable $(ARCHFLAGS)" ABC_USE_NO_READLINE=1
ifeq ($(DISABLE_ABC_THREADS),1)
ABCMKARGS += "ABC_USE_NO_PTHREADS=1"
endif
else ifeq ($(CONFIG),gcc-4.8) else ifeq ($(CONFIG),gcc-4.8)
CXX = gcc-4.8 CXX = gcc-4.8
LD = gcc-4.8 LD = gcc-4.8
@ -199,14 +212,14 @@ yosys.html: misc/yosys.html
else ifeq ($(CONFIG),mxe) else ifeq ($(CONFIG),mxe)
PKG_CONFIG = /usr/local/src/mxe/usr/bin/i686-w64-mingw32.static-pkg-config PKG_CONFIG = /usr/local/src/mxe/usr/bin/i686-w64-mingw32.static-pkg-config
CXX = /usr/local/src/mxe/usr/bin/i686-w64-mingw32.static-gcc CXX = /usr/local/src/mxe/usr/bin/i686-w64-mingw32.static-g++
LD = /usr/local/src/mxe/usr/bin/i686-w64-mingw32.static-gcc LD = /usr/local/src/mxe/usr/bin/i686-w64-mingw32.static-g++
CXXFLAGS += -std=c++11 -Os -D_POSIX_SOURCE -DYOSYS_MXE_HACKS -Wno-attributes CXXFLAGS += -std=c++11 -Os -D_POSIX_SOURCE -DYOSYS_MXE_HACKS -Wno-attributes
CXXFLAGS := $(filter-out -fPIC,$(CXXFLAGS)) CXXFLAGS := $(filter-out -fPIC,$(CXXFLAGS))
LDFLAGS := $(filter-out -rdynamic,$(LDFLAGS)) -s LDFLAGS := $(filter-out -rdynamic,$(LDFLAGS)) -s
LDLIBS := $(filter-out -lrt,$(LDLIBS)) LDLIBS := $(filter-out -lrt,$(LDLIBS))
ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H -DWIN32_NO_DLL -DHAVE_STRUCT_TIMESPEC -fpermissive -w" ABCMKARGS += ARCHFLAGS="-DWIN32_NO_DLL -DHAVE_STRUCT_TIMESPEC -fpermissive -w"
ABCMKARGS += LIBS="lib/x86/pthreadVC2.lib -s" ABC_USE_NO_READLINE=1 ABCMKARGS += LIBS="lib/x86/pthreadVC2.lib -s" ABC_USE_NO_READLINE=1 CC="/usr/local/src/mxe/usr/bin/i686-w64-mingw32.static-gcc"
EXE = .exe EXE = .exe
else ifeq ($(CONFIG),msys2) else ifeq ($(CONFIG),msys2)
@ -217,11 +230,22 @@ CXXFLAGS := $(filter-out -fPIC,$(CXXFLAGS))
LDFLAGS := $(filter-out -rdynamic,$(LDFLAGS)) -s LDFLAGS := $(filter-out -rdynamic,$(LDFLAGS)) -s
LDLIBS := $(filter-out -lrt,$(LDLIBS)) LDLIBS := $(filter-out -lrt,$(LDLIBS))
ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H -DWIN32_NO_DLL -DHAVE_STRUCT_TIMESPEC -fpermissive -w" ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H -DWIN32_NO_DLL -DHAVE_STRUCT_TIMESPEC -fpermissive -w"
ABCMKARGS += LIBS="lib/x86/pthreadVC2.lib -s" ABC_USE_NO_READLINE=0 ABCMKARGS += LIBS="-lpthread -s" ABC_USE_NO_READLINE=0 CC="i686-w64-mingw32-gcc" CXX="$(CXX)"
EXE = .exe
else ifeq ($(CONFIG),msys2-64)
CXX = x86_64-w64-mingw32-g++
LD = x86_64-w64-mingw32-g++
CXXFLAGS += -std=c++11 -Os -D_POSIX_SOURCE -DYOSYS_WIN32_UNIX_DIR
CXXFLAGS := $(filter-out -fPIC,$(CXXFLAGS))
LDFLAGS := $(filter-out -rdynamic,$(LDFLAGS)) -s
LDLIBS := $(filter-out -lrt,$(LDLIBS))
ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H -DWIN32_NO_DLL -DHAVE_STRUCT_TIMESPEC -fpermissive -w"
ABCMKARGS += LIBS="-lpthread -s" ABC_USE_NO_READLINE=0 CC="x86_64-w64-mingw32-gcc" CXX="$(CXX)"
EXE = .exe EXE = .exe
else ifneq ($(CONFIG),none) else ifneq ($(CONFIG),none)
$(error Invalid CONFIG setting '$(CONFIG)'. Valid values: clang, gcc, gcc-4.8, emcc, mxe, msys2) $(error Invalid CONFIG setting '$(CONFIG)'. Valid values: clang, gcc, gcc-4.8, emcc, mxe, msys2, msys2-64)
endif endif
ifeq ($(ENABLE_LIBYOSYS),1) ifeq ($(ENABLE_LIBYOSYS),1)
@ -276,7 +300,7 @@ endif
ifeq ($(CONFIG),mxe) ifeq ($(CONFIG),mxe)
CXXFLAGS += -DYOSYS_ENABLE_TCL CXXFLAGS += -DYOSYS_ENABLE_TCL
LDLIBS += -ltcl86 -lwsock32 -lws2_32 -lnetapi32 LDLIBS += -ltcl86 -lwsock32 -lws2_32 -lnetapi32 -lz
else else
CXXFLAGS += $(shell PKG_CONFIG_PATH=$(PKG_CONFIG_PATH) $(PKG_CONFIG) --silence-errors --cflags tcl || echo -I$(TCL_INCLUDE)) -DYOSYS_ENABLE_TCL CXXFLAGS += $(shell PKG_CONFIG_PATH=$(PKG_CONFIG_PATH) $(PKG_CONFIG) --silence-errors --cflags tcl || echo -I$(TCL_INCLUDE)) -DYOSYS_ENABLE_TCL
ifeq ($(OS), FreeBSD) ifeq ($(OS), FreeBSD)
@ -659,6 +683,12 @@ config-clang: clean
config-gcc: clean config-gcc: clean
echo 'CONFIG := gcc' > Makefile.conf echo 'CONFIG := gcc' > Makefile.conf
config-gcc-static: clean
echo 'CONFIG := gcc-static' > Makefile.conf
echo 'ENABLE_PLUGINS := 0' >> Makefile.conf
echo 'ENABLE_READLINE := 0' >> Makefile.conf
echo 'ENABLE_TCL := 0' >> Makefile.conf
config-gcc-4.8: clean config-gcc-4.8: clean
echo 'CONFIG := gcc-4.8' > Makefile.conf echo 'CONFIG := gcc-4.8' > Makefile.conf
@ -676,6 +706,9 @@ config-mxe: clean
config-msys2: clean config-msys2: clean
echo 'CONFIG := msys2' > Makefile.conf echo 'CONFIG := msys2' > Makefile.conf
config-msys2-64: clean
echo 'CONFIG := msys2-64' > Makefile.conf
config-gprof: clean config-gprof: clean
echo 'CONFIG := gcc' > Makefile.conf echo 'CONFIG := gcc' > Makefile.conf
echo 'ENABLE_GPROF := 1' >> Makefile.conf echo 'ENABLE_GPROF := 1' >> Makefile.conf
@ -697,5 +730,5 @@ echo-git-rev:
-include techlibs/*/*.d -include techlibs/*/*.d
.PHONY: all top-all abc test install install-abc manual clean mrproper qtcreator .PHONY: all top-all abc test install install-abc manual clean mrproper qtcreator
.PHONY: config-clean config-clang config-gcc config-gcc-4.8 config-gprof config-sudo .PHONY: config-clean config-clang config-gcc config-gcc-static config-gcc-4.8 config-gprof config-sudo

2
README.md
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@ -389,7 +389,7 @@ Verilog Attributes and non-standard features
Non-standard or SystemVerilog features for formal verification Non-standard or SystemVerilog features for formal verification
============================================================== ==============================================================
- Support for ``assert``, ``assume``, ``restrict``, and ``cover'' is enabled - Support for ``assert``, ``assume``, ``restrict``, and ``cover`` is enabled
when ``read_verilog`` is called with ``-formal``. when ``read_verilog`` is called with ``-formal``.
- The system task ``$initstate`` evaluates to 1 in the initial state and - The system task ``$initstate`` evaluates to 1 in the initial state and

4
backends/aiger/aiger.cc
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@ -657,7 +657,7 @@ struct AigerWriter
struct AigerBackend : public Backend { struct AigerBackend : public Backend {
AigerBackend() : Backend("aiger", "write design to AIGER file") { } AigerBackend() : Backend("aiger", "write design to AIGER file") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -690,7 +690,7 @@ struct AigerBackend : public Backend {
log(" like -map, but more verbose\n"); log(" like -map, but more verbose\n");
log("\n"); log("\n");
} }
virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
bool ascii_mode = false; bool ascii_mode = false;
bool zinit_mode = false; bool zinit_mode = false;

4
backends/blif/blif.cc
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@ -464,7 +464,7 @@ struct BlifDumper
struct BlifBackend : public Backend { struct BlifBackend : public Backend {
BlifBackend() : Backend("blif", "write design to BLIF file") { } BlifBackend() : Backend("blif", "write design to BLIF file") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -534,7 +534,7 @@ struct BlifBackend : public Backend {
log(" do not write definitions for the $true, $false and $undef wires.\n"); log(" do not write definitions for the $true, $false and $undef wires.\n");
log("\n"); log("\n");
} }
virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
std::string top_module_name; std::string top_module_name;
std::string buf_type, buf_in, buf_out; std::string buf_type, buf_in, buf_out;

4
backends/btor/btor.cc
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@ -1076,7 +1076,7 @@ struct BtorWorker
struct BtorBackend : public Backend { struct BtorBackend : public Backend {
BtorBackend() : Backend("btor", "write design to BTOR file") { } BtorBackend() : Backend("btor", "write design to BTOR file") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -1091,7 +1091,7 @@ struct BtorBackend : public Backend {
log(" Output only a single bad property for all asserts\n"); log(" Output only a single bad property for all asserts\n");
log("\n"); log("\n");
} }
virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
bool verbose = false, single_bad = false; bool verbose = false, single_bad = false;

4
backends/edif/edif.cc
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@ -90,7 +90,7 @@ struct EdifNames
struct EdifBackend : public Backend { struct EdifBackend : public Backend {
EdifBackend() : Backend("edif", "write design to EDIF netlist file") { } EdifBackend() : Backend("edif", "write design to EDIF netlist file") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -116,7 +116,7 @@ struct EdifBackend : public Backend {
log("is targeted.\n"); log("is targeted.\n");
log("\n"); log("\n");
} }
virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
log_header(design, "Executing EDIF backend.\n"); log_header(design, "Executing EDIF backend.\n");
std::string top_module_name; std::string top_module_name;

4
backends/firrtl/firrtl.cc
View File

@ -527,7 +527,7 @@ struct FirrtlWorker
struct FirrtlBackend : public Backend { struct FirrtlBackend : public Backend {
FirrtlBackend() : Backend("firrtl", "write design to a FIRRTL file") { } FirrtlBackend() : Backend("firrtl", "write design to a FIRRTL file") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -536,7 +536,7 @@ struct FirrtlBackend : public Backend {
log("Write a FIRRTL netlist of the current design.\n"); log("Write a FIRRTL netlist of the current design.\n");
log("\n"); log("\n");
} }
virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
size_t argidx; size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) for (argidx = 1; argidx < args.size(); argidx++)

8
backends/ilang/ilang_backend.cc
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@ -382,7 +382,7 @@ PRIVATE_NAMESPACE_BEGIN
struct IlangBackend : public Backend { struct IlangBackend : public Backend {
IlangBackend() : Backend("ilang", "write design to ilang file") { } IlangBackend() : Backend("ilang", "write design to ilang file") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -395,7 +395,7 @@ struct IlangBackend : public Backend {
log(" only write selected parts of the design.\n"); log(" only write selected parts of the design.\n");
log("\n"); log("\n");
} }
virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
bool selected = false; bool selected = false;
@ -422,7 +422,7 @@ struct IlangBackend : public Backend {
struct DumpPass : public Pass { struct DumpPass : public Pass {
DumpPass() : Pass("dump", "print parts of the design in ilang format") { } DumpPass() : Pass("dump", "print parts of the design in ilang format") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -445,7 +445,7 @@ struct DumpPass : public Pass {
log(" like -outfile but append instead of overwrite\n"); log(" like -outfile but append instead of overwrite\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
std::string filename; std::string filename;
bool flag_m = false, flag_n = false, append = false; bool flag_m = false, flag_n = false, append = false;

4
backends/intersynth/intersynth.cc
View File

@ -46,7 +46,7 @@ static std::string netname(std::set<std::string> &conntypes_code, std::set<std::
struct IntersynthBackend : public Backend { struct IntersynthBackend : public Backend {
IntersynthBackend() : Backend("intersynth", "write design to InterSynth netlist file") { } IntersynthBackend() : Backend("intersynth", "write design to InterSynth netlist file") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -71,7 +71,7 @@ struct IntersynthBackend : public Backend {
log("http://www.clifford.at/intersynth/\n"); log("http://www.clifford.at/intersynth/\n");
log("\n"); log("\n");
} }
virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
log_header(design, "Executing INTERSYNTH backend.\n"); log_header(design, "Executing INTERSYNTH backend.\n");
log_push(); log_push();

12
backends/json/json.cc
View File

@ -93,8 +93,10 @@ struct JsonWriter
f << get_string(param.second.decode_string()); f << get_string(param.second.decode_string());
else if (GetSize(param.second.bits) > 32) else if (GetSize(param.second.bits) > 32)
f << get_string(param.second.as_string()); f << get_string(param.second.as_string());
else else if ((param.second.flags & RTLIL::ConstFlags::CONST_FLAG_SIGNED) != 0)
f << stringf("%d", param.second.as_int()); f << stringf("%d", param.second.as_int());
else
f << stringf("%u", param.second.as_int());
first = false; first = false;
} }
} }
@ -250,7 +252,7 @@ struct JsonWriter
struct JsonBackend : public Backend { struct JsonBackend : public Backend {
JsonBackend() : Backend("json", "write design to a JSON file") { } JsonBackend() : Backend("json", "write design to a JSON file") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -458,7 +460,7 @@ struct JsonBackend : public Backend {
log("format. A program processing this format must ignore all unknown fields.\n"); log("format. A program processing this format must ignore all unknown fields.\n");
log("\n"); log("\n");
} }
virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
bool aig_mode = false; bool aig_mode = false;
@ -482,7 +484,7 @@ struct JsonBackend : public Backend {
struct JsonPass : public Pass { struct JsonPass : public Pass {
JsonPass() : Pass("json", "write design in JSON format") { } JsonPass() : Pass("json", "write design in JSON format") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -499,7 +501,7 @@ struct JsonPass : public Pass {
log("See 'help write_json' for a description of the JSON format used.\n"); log("See 'help write_json' for a description of the JSON format used.\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
std::string filename; std::string filename;
bool aig_mode = false; bool aig_mode = false;

8
backends/protobuf/protobuf.cc
View File

@ -231,7 +231,7 @@ struct ProtobufDesignSerializer
struct ProtobufBackend : public Backend { struct ProtobufBackend : public Backend {
ProtobufBackend(): Backend("protobuf", "write design to a Protocol Buffer file") { } ProtobufBackend(): Backend("protobuf", "write design to a Protocol Buffer file") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -249,7 +249,7 @@ struct ProtobufBackend : public Backend {
log("Yosys source code distribution.\n"); log("Yosys source code distribution.\n");
log("\n"); log("\n");
} }
virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
bool aig_mode = false; bool aig_mode = false;
bool text_mode = false; bool text_mode = false;
@ -286,7 +286,7 @@ struct ProtobufBackend : public Backend {
struct ProtobufPass : public Pass { struct ProtobufPass : public Pass {
ProtobufPass() : Pass("protobuf", "write design in Protobuf format") { } ProtobufPass() : Pass("protobuf", "write design in Protobuf format") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -307,7 +307,7 @@ struct ProtobufPass : public Pass {
log("Yosys source code distribution.\n"); log("Yosys source code distribution.\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
std::string filename; std::string filename;
bool aig_mode = false; bool aig_mode = false;

4
backends/simplec/simplec.cc
View File

@ -742,7 +742,7 @@ struct SimplecWorker
struct SimplecBackend : public Backend { struct SimplecBackend : public Backend {
SimplecBackend() : Backend("simplec", "convert design to simple C code") { } SimplecBackend() : Backend("simplec", "convert design to simple C code") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -761,7 +761,7 @@ struct SimplecBackend : public Backend {
log("THIS COMMAND IS UNDER CONSTRUCTION\n"); log("THIS COMMAND IS UNDER CONSTRUCTION\n");
log("\n"); log("\n");
} }
virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
reserved_cids.clear(); reserved_cids.clear();
id2cid.clear(); id2cid.clear();

2
backends/smt2/Makefile.inc
View File

@ -6,7 +6,7 @@ ifneq ($(CONFIG),emcc)
TARGETS += yosys-smtbmc TARGETS += yosys-smtbmc
yosys-smtbmc: backends/smt2/smtbmc.py yosys-smtbmc: backends/smt2/smtbmc.py
$(P) sed 's|##yosys-sys-path##|sys.path += [os.path.dirname(__file__) + p for p in ["/share/python3", "/../share/yosys/python3"]]|;' < $< > $@.new $(P) sed 's|##yosys-sys-path##|sys.path += [os.path.dirname(os.path.realpath(__file__)) + p for p in ["/share/python3", "/../share/yosys/python3"]]|;' < $< > $@.new
$(Q) chmod +x $@.new $(Q) chmod +x $@.new
$(Q) mv $@.new $@ $(Q) mv $@.new $@

4
backends/smt2/smt2.cc
View File

@ -1251,7 +1251,7 @@ struct Smt2Worker
struct Smt2Backend : public Backend { struct Smt2Backend : public Backend {
Smt2Backend() : Backend("smt2", "write design to SMT-LIBv2 file") { } Smt2Backend() : Backend("smt2", "write design to SMT-LIBv2 file") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -1407,7 +1407,7 @@ struct Smt2Backend : public Backend {
log("from non-zero to zero in the test design.\n"); log("from non-zero to zero in the test design.\n");
log("\n"); log("\n");
} }
virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
std::ifstream template_f; std::ifstream template_f;
bool bvmode = true, memmode = true, wiresmode = false, verbose = false, statebv = false, statedt = false; bool bvmode = true, memmode = true, wiresmode = false, verbose = false, statebv = false, statedt = false;

21
backends/smt2/smtio.py
View File

@ -17,7 +17,9 @@
# #
import sys, re, os, signal import sys, re, os, signal
import resource, subprocess import subprocess
if os.name == "posix":
import resource
from copy import deepcopy from copy import deepcopy
from select import select from select import select
from time import time from time import time
@ -27,12 +29,13 @@ from threading import Thread
# This is needed so that the recursive SMT2 S-expression parser # This is needed so that the recursive SMT2 S-expression parser
# does not run out of stack frames when parsing large expressions # does not run out of stack frames when parsing large expressions
smtio_reclimit = 64 * 1024 if os.name == "posix":
smtio_stacksize = 128 * 1024 * 1024 smtio_reclimit = 64 * 1024
if sys.getrecursionlimit() < smtio_reclimit: smtio_stacksize = 128 * 1024 * 1024
sys.setrecursionlimit(smtio_reclimit) if sys.getrecursionlimit() < smtio_reclimit:
if resource.getrlimit(resource.RLIMIT_STACK)[0] < smtio_stacksize: sys.setrecursionlimit(smtio_reclimit)
resource.setrlimit(resource.RLIMIT_STACK, (smtio_stacksize, -1)) if resource.getrlimit(resource.RLIMIT_STACK)[0] < smtio_stacksize:
resource.setrlimit(resource.RLIMIT_STACK, (smtio_stacksize, -1))
# currently running solvers (so we can kill them) # currently running solvers (so we can kill them)
@ -51,8 +54,9 @@ def force_shutdown(signum, frame):
os.kill(p.pid, signal.SIGTERM) os.kill(p.pid, signal.SIGTERM)
sys.exit(1) sys.exit(1)
if os.name == "posix":
signal.signal(signal.SIGHUP, force_shutdown)
signal.signal(signal.SIGINT, force_shutdown) signal.signal(signal.SIGINT, force_shutdown)
signal.signal(signal.SIGHUP, force_shutdown)
signal.signal(signal.SIGTERM, force_shutdown) signal.signal(signal.SIGTERM, force_shutdown)
def except_hook(exctype, value, traceback): def except_hook(exctype, value, traceback):
@ -1053,4 +1057,3 @@ class MkVcd:
print("b0 %s" % self.nets[path][0], file=self.f) print("b0 %s" % self.nets[path][0], file=self.f)
else: else:
print("b1 %s" % self.nets[path][0], file=self.f) print("b1 %s" % self.nets[path][0], file=self.f)

4
backends/smv/smv.cc
View File

@ -675,7 +675,7 @@ struct SmvWorker
struct SmvBackend : public Backend { struct SmvBackend : public Backend {
SmvBackend() : Backend("smv", "write design to SMV file") { } SmvBackend() : Backend("smv", "write design to SMV file") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -693,7 +693,7 @@ struct SmvBackend : public Backend {
log("THIS COMMAND IS UNDER CONSTRUCTION\n"); log("THIS COMMAND IS UNDER CONSTRUCTION\n");
log("\n"); log("\n");
} }
virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
std::ifstream template_f; std::ifstream template_f;
bool verbose = false; bool verbose = false;

4
backends/spice/spice.cc
View File

@ -132,7 +132,7 @@ static void print_spice_module(std::ostream &f, RTLIL::Module *module, RTLIL::De
struct SpiceBackend : public Backend { struct SpiceBackend : public Backend {
SpiceBackend() : Backend("spice", "write design to SPICE netlist file") { } SpiceBackend() : Backend("spice", "write design to SPICE netlist file") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -161,7 +161,7 @@ struct SpiceBackend : public Backend {
log(" set the specified module as design top module\n"); log(" set the specified module as design top module\n");
log("\n"); log("\n");
} }
virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
std::string top_module_name; std::string top_module_name;
RTLIL::Module *top_module = NULL; RTLIL::Module *top_module = NULL;

4
backends/table/table.cc
View File

@ -29,7 +29,7 @@ PRIVATE_NAMESPACE_BEGIN
struct TableBackend : public Backend { struct TableBackend : public Backend {
TableBackend() : Backend("table", "write design as connectivity table") { } TableBackend() : Backend("table", "write design as connectivity table") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -48,7 +48,7 @@ struct TableBackend : public Backend {
log("module inputs and outputs are output using cell type and port '-' and with\n"); log("module inputs and outputs are output using cell type and port '-' and with\n");
log("'pi' (primary input) or 'po' (primary output) or 'pio' as direction.\n"); log("'pi' (primary input) or 'po' (primary output) or 'pio' as direction.\n");
} }
virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
log_header(design, "Executing TABLE backend.\n"); log_header(design, "Executing TABLE backend.\n");

4
backends/verilog/verilog_backend.cc
View File

@ -1482,7 +1482,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
struct VerilogBackend : public Backend { struct VerilogBackend : public Backend {
VerilogBackend() : Backend("verilog", "write design to Verilog file") { } VerilogBackend() : Backend("verilog", "write design to Verilog file") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -1550,7 +1550,7 @@ struct VerilogBackend : public Backend {
log("this command is called on a design with RTLIL processes.\n"); log("this command is called on a design with RTLIL processes.\n");
log("\n"); log("\n");
} }
virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
log_header(design, "Executing Verilog backend.\n"); log_header(design, "Executing Verilog backend.\n");

3
examples/basys3/example.xdc
View File

@ -19,3 +19,6 @@ set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN L1 } [get_ports {LD[15]}]
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK] create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

1
examples/basys3/run_prog.tcl
View File

@ -1,3 +1,4 @@
open_hw
connect_hw_server connect_hw_server
open_hw_target [lindex [get_hw_targets] 0] open_hw_target [lindex [get_hw_targets] 0]
set_property PROGRAM.FILE example.bit [lindex [get_hw_devices] 0] set_property PROGRAM.FILE example.bit [lindex [get_hw_devices] 0]

2
examples/cxx-api/evaldemo.cc
View File

@ -22,7 +22,7 @@ struct EvalDemoPass : public Pass
{ {
EvalDemoPass() : Pass("evaldemo") { } EvalDemoPass() : Pass("evaldemo") { }
virtual void execute(vector<string>, Design *design) void execute(vector<string>, Design *design) YS_OVERRIDE
{ {
Module *module = design->top_module(); Module *module = design->top_module();

21
frontends/ast/ast.cc
View File

@ -171,8 +171,8 @@ bool AstNode::get_bool_attribute(RTLIL::IdString id)
AstNode *attr = attributes.at(id); AstNode *attr = attributes.at(id);
if (attr->type != AST_CONSTANT) if (attr->type != AST_CONSTANT)
log_error("Attribute `%s' with non-constant value at %s:%d!\n", log_file_error(attr->filename, attr->linenum, "Attribute `%s' with non-constant value!\n",
id.c_str(), attr->filename.c_str(), attr->linenum); id.c_str());
return attr->integer != 0; return attr->integer != 0;
} }
@ -191,8 +191,10 @@ AstNode::AstNode(AstNodeType type, AstNode *child1, AstNode *child2, AstNode *ch
is_input = false; is_input = false;
is_output = false; is_output = false;
is_reg = false; is_reg = false;
is_logic = false;
is_signed = false; is_signed = false;
is_string = false; is_string = false;
was_checked = false;
range_valid = false; range_valid = false;
range_swapped = false; range_swapped = false;
port_id = 0; port_id = 0;
@ -285,7 +287,9 @@ void AstNode::dumpAst(FILE *f, std::string indent) const
fprintf(f, " input"); fprintf(f, " input");
if (is_output) if (is_output)
fprintf(f, " output"); fprintf(f, " output");
if (is_reg) if (is_logic)
fprintf(f, " logic");
if (is_reg) // this is an AST dump, not Verilog - if we see "logic reg" that's fine.
fprintf(f, " reg"); fprintf(f, " reg");
if (is_signed) if (is_signed)
fprintf(f, " signed"); fprintf(f, " signed");
@ -652,6 +656,8 @@ bool AstNode::operator==(const AstNode &other) const
return false; return false;
if (is_output != other.is_output) if (is_output != other.is_output)
return false; return false;
if (is_logic != other.is_logic)
return false;
if (is_reg != other.is_reg) if (is_reg != other.is_reg)
return false; return false;
if (is_signed != other.is_signed) if (is_signed != other.is_signed)
@ -955,8 +961,8 @@ static AstModule* process_module(AstNode *ast, bool defer)
for (auto &attr : ast->attributes) { for (auto &attr : ast->attributes) {
if (attr.second->type != AST_CONSTANT) if (attr.second->type != AST_CONSTANT)
log_error("Attribute `%s' with non-constant value at %s:%d!\n", log_file_error(ast->filename, ast->linenum, "Attribute `%s' with non-constant value!\n",
attr.first.c_str(), ast->filename.c_str(), ast->linenum); attr.first.c_str());
current_module->attributes[attr.first] = attr.second->asAttrConst(); current_module->attributes[attr.first] = attr.second->asAttrConst();
} }
for (size_t i = 0; i < ast->children.size(); i++) { for (size_t i = 0; i < ast->children.size(); i++) {
@ -1044,8 +1050,8 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
if (design->has((*it)->str)) { if (design->has((*it)->str)) {
RTLIL::Module *existing_mod = design->module((*it)->str); RTLIL::Module *existing_mod = design->module((*it)->str);
if (!nooverwrite && !overwrite && !existing_mod->get_bool_attribute("\\blackbox")) { if (!nooverwrite && !overwrite && !existing_mod->get_bool_attribute("\\blackbox")) {
log_error("Re-definition of module `%s' at %s:%d!\n", log_file_error((*it)->filename, (*it)->linenum, "Re-definition of module `%s'!\n",
(*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum); (*it)->str.c_str());
} else if (nooverwrite) { } else if (nooverwrite) {
log("Ignoring re-definition of module `%s' at %s:%d.\n", log("Ignoring re-definition of module `%s' at %s:%d.\n",
(*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum); (*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum);
@ -1197,4 +1203,3 @@ void AST::use_internal_line_num()
} }
YOSYS_NAMESPACE_END YOSYS_NAMESPACE_END

10
frontends/ast/ast.h
View File

@ -1,4 +1,4 @@
/* /* -*- c++ -*-
* yosys -- Yosys Open SYnthesis Suite * yosys -- Yosys Open SYnthesis Suite
* *
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
@ -168,7 +168,7 @@ namespace AST
// node content - most of it is unused in most node types // node content - most of it is unused in most node types
std::string str; std::string str;
std::vector<RTLIL::State> bits; std::vector<RTLIL::State> bits;
bool is_input, is_output, is_reg, is_signed, is_string, range_valid, range_swapped; bool is_input, is_output, is_reg, is_logic, is_signed, is_string, range_valid, range_swapped, was_checked;
int port_id, range_left, range_right; int port_id, range_left, range_right;
uint32_t integer; uint32_t integer;
double realvalue; double realvalue;
@ -282,9 +282,9 @@ namespace AST
struct AstModule : RTLIL::Module { struct AstModule : RTLIL::Module {
AstNode *ast; AstNode *ast;
bool nolatches, nomeminit, nomem2reg, mem2reg, lib, noopt, icells, autowire; bool nolatches, nomeminit, nomem2reg, mem2reg, lib, noopt, icells, autowire;
virtual ~AstModule(); ~AstModule() YS_OVERRIDE;
virtual RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, bool mayfail); RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, bool mayfail) YS_OVERRIDE;
virtual RTLIL::Module *clone() const; RTLIL::Module *clone() const YS_OVERRIDE;
}; };
// this must be set by the language frontend before parsing the sources // this must be set by the language frontend before parsing the sources

177
frontends/ast/genrtlil.cc
View File

@ -55,8 +55,8 @@ static RTLIL::SigSpec uniop2rtlil(AstNode *that, std::string type, int result_wi
if (gen_attributes) if (gen_attributes)
for (auto &attr : that->attributes) { for (auto &attr : that->attributes) {
if (attr.second->type != AST_CONSTANT) if (attr.second->type != AST_CONSTANT)
log_error("Attribute `%s' with non-constant value at %s:%d!\n", log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n",
attr.first.c_str(), that->filename.c_str(), that->linenum); attr.first.c_str());
cell->attributes[attr.first] = attr.second->asAttrConst(); cell->attributes[attr.first] = attr.second->asAttrConst();
} }
@ -89,8 +89,8 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
if (that != NULL) if (that != NULL)
for (auto &attr : that->attributes) { for (auto &attr : that->attributes) {
if (attr.second->type != AST_CONSTANT) if (attr.second->type != AST_CONSTANT)
log_error("Attribute `%s' with non-constant value at %s:%d!\n", log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n",
attr.first.c_str(), that->filename.c_str(), that->linenum); attr.first.c_str());
cell->attributes[attr.first] = attr.second->asAttrConst(); cell->attributes[attr.first] = attr.second->asAttrConst();
} }
@ -117,8 +117,8 @@ static RTLIL::SigSpec binop2rtlil(AstNode *that, std::string type, int result_wi
for (auto &attr : that->attributes) { for (auto &attr : that->attributes) {
if (attr.second->type != AST_CONSTANT) if (attr.second->type != AST_CONSTANT)
log_error("Attribute `%s' with non-constant value at %s:%d!\n", log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n",
attr.first.c_str(), that->filename.c_str(), that->linenum); attr.first.c_str());
cell->attributes[attr.first] = attr.second->asAttrConst(); cell->attributes[attr.first] = attr.second->asAttrConst();
} }
@ -152,8 +152,8 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const
for (auto &attr : that->attributes) { for (auto &attr : that->attributes) {
if (attr.second->type != AST_CONSTANT) if (attr.second->type != AST_CONSTANT)
log_error("Attribute `%s' with non-constant value at %s:%d!\n", log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n",
attr.first.c_str(), that->filename.c_str(), that->linenum); attr.first.c_str());
cell->attributes[attr.first] = attr.second->asAttrConst(); cell->attributes[attr.first] = attr.second->asAttrConst();
} }
@ -207,8 +207,8 @@ struct AST_INTERNAL::ProcessGenerator
proc->name = stringf("$proc$%s:%d$%d", always->filename.c_str(), always->linenum, autoidx++); proc->name = stringf("$proc$%s:%d$%d", always->filename.c_str(), always->linenum, autoidx++);
for (auto &attr : always->attributes) { for (auto &attr : always->attributes) {
if (attr.second->type != AST_CONSTANT) if (attr.second->type != AST_CONSTANT)
log_error("Attribute `%s' with non-constant value at %s:%d!\n", log_file_error(always->filename, always->linenum, "Attribute `%s' with non-constant value!\n",
attr.first.c_str(), always->filename.c_str(), always->linenum); attr.first.c_str());
proc->attributes[attr.first] = attr.second->asAttrConst(); proc->attributes[attr.first] = attr.second->asAttrConst();
} }
current_module->processes[proc->name] = proc; current_module->processes[proc->name] = proc;
@ -238,7 +238,7 @@ struct AST_INTERNAL::ProcessGenerator
if (found_anyedge_syncs) { if (found_anyedge_syncs) {
if (found_global_syncs) if (found_global_syncs)
log_error("Found non-synthesizable event list at %s:%d!\n", always->filename.c_str(), always->linenum); log_file_error(always->filename, always->linenum, "Found non-synthesizable event list!\n");
log("Note: Assuming pure combinatorial block at %s:%d in\n", always->filename.c_str(), always->linenum); log("Note: Assuming pure combinatorial block at %s:%d in\n", always->filename.c_str(), always->linenum);
log("compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending\n"); log("compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending\n");
log("use of @* instead of @(...) for better match of synthesis and simulation.\n"); log("use of @* instead of @(...) for better match of synthesis and simulation.\n");
@ -253,12 +253,12 @@ struct AST_INTERNAL::ProcessGenerator
continue; continue;
found_clocked_sync = true; found_clocked_sync = true;
if (found_global_syncs || found_anyedge_syncs) if (found_global_syncs || found_anyedge_syncs)
log_error("Found non-synthesizable event list at %s:%d!\n", always->filename.c_str(), always->linenum); log_file_error(always->filename, always->linenum, "Found non-synthesizable event list!\n");
RTLIL::SyncRule *syncrule = new RTLIL::SyncRule; RTLIL::SyncRule *syncrule = new RTLIL::SyncRule;
syncrule->type = child->type == AST_POSEDGE ? RTLIL::STp : RTLIL::STn; syncrule->type = child->type == AST_POSEDGE ? RTLIL::STp : RTLIL::STn;
syncrule->signal = child->children[0]->genRTLIL(); syncrule->signal = child->children[0]->genRTLIL();
if (GetSize(syncrule->signal) != 1) if (GetSize(syncrule->signal) != 1)
log_error("Found posedge/negedge event on a signal that is not 1 bit wide at %s:%d!\n", always->filename.c_str(), always->linenum); log_file_error(always->filename, always->linenum, "Found posedge/negedge event on a signal that is not 1 bit wide!\n");
addChunkActions(syncrule->actions, subst_lvalue_from, subst_lvalue_to, true); addChunkActions(syncrule->actions, subst_lvalue_from, subst_lvalue_to, true);
proc->syncs.push_back(syncrule); proc->syncs.push_back(syncrule);
} }
@ -480,8 +480,8 @@ struct AST_INTERNAL::ProcessGenerator
for (auto &attr : ast->attributes) { for (auto &attr : ast->attributes) {
if (attr.second->type != AST_CONSTANT) if (attr.second->type != AST_CONSTANT)
log_error("Attribute `%s' with non-constant value at %s:%d!\n", log_file_error(ast->filename, ast->linenum, "Attribute `%s' with non-constant value!\n",
attr.first.c_str(), ast->filename.c_str(), ast->linenum); attr.first.c_str());
sw->attributes[attr.first] = attr.second->asAttrConst(); sw->attributes[attr.first] = attr.second->asAttrConst();
} }
@ -549,12 +549,12 @@ struct AST_INTERNAL::ProcessGenerator
break; break;
case AST_WIRE: case AST_WIRE:
log_error("Found wire declaration in block without label at at %s:%d!\n", ast->filename.c_str(), ast->linenum); log_file_error(ast->filename, ast->linenum, "Found wire declaration in block without label!\n");
break; break;
case AST_PARAMETER: case AST_PARAMETER:
case AST_LOCALPARAM: case AST_LOCALPARAM:
log_error("Found parameter declaration in block without label at at %s:%d!\n", ast->filename.c_str(), ast->linenum); log_file_error(ast->filename, ast->linenum, "Found parameter declaration in block without label!\n");
break; break;
case AST_NONE: case AST_NONE:
@ -602,7 +602,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
if (id_ast == NULL && current_scope.count(str)) if (id_ast == NULL && current_scope.count(str))
id_ast = current_scope.at(str); id_ast = current_scope.at(str);
if (!id_ast) if (!id_ast)
log_error("Failed to resolve identifier %s for width detection at %s:%d!\n", str.c_str(), filename.c_str(), linenum); log_file_error(filename, linenum, "Failed to resolve identifier %s for width detection!\n", str.c_str());
if (id_ast->type == AST_PARAMETER || id_ast->type == AST_LOCALPARAM) { if (id_ast->type == AST_PARAMETER || id_ast->type == AST_LOCALPARAM) {
if (id_ast->children.size() > 1 && id_ast->children[1]->range_valid) { if (id_ast->children.size() > 1 && id_ast->children[1]->range_valid) {
this_width = id_ast->children[1]->range_left - id_ast->children[1]->range_right + 1; this_width = id_ast->children[1]->range_left - id_ast->children[1]->range_right + 1;
@ -612,7 +612,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
if (id_ast->children[0]->type == AST_CONSTANT) if (id_ast->children[0]->type == AST_CONSTANT)
this_width = id_ast->children[0]->bits.size(); this_width = id_ast->children[0]->bits.size();
else else
log_error("Failed to detect width for parameter %s at %s:%d!\n", str.c_str(), filename.c_str(), linenum); log_file_error(filename, linenum, "Failed to detect width for parameter %s!\n", str.c_str());
if (children.size() != 0) if (children.size() != 0)
range = children[0]; range = children[0];
} else if (id_ast->type == AST_WIRE || id_ast->type == AST_AUTOWIRE) { } else if (id_ast->type == AST_WIRE || id_ast->type == AST_AUTOWIRE) {
@ -624,7 +624,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
// log("---\n"); // log("---\n");
// id_ast->dumpAst(NULL, "decl> "); // id_ast->dumpAst(NULL, "decl> ");
// dumpAst(NULL, "ref> "); // dumpAst(NULL, "ref> ");
log_error("Failed to detect width of signal access `%s' at %s:%d!\n", str.c_str(), filename.c_str(), linenum); log_file_error(filename, linenum, "Failed to detect width of signal access `%s'!\n", str.c_str());
} }
} else { } else {
this_width = id_ast->range_left - id_ast->range_right + 1; this_width = id_ast->range_left - id_ast->range_right + 1;
@ -635,10 +635,10 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
this_width = 32; this_width = 32;
} else if (id_ast->type == AST_MEMORY) { } else if (id_ast->type == AST_MEMORY) {
if (!id_ast->children[0]->range_valid) if (!id_ast->children[0]->range_valid)
log_error("Failed to detect width of memory access `%s' at %s:%d!\n", str.c_str(), filename.c_str(), linenum); log_file_error(filename, linenum, "Failed to detect width of memory access `%s'!\n", str.c_str());
this_width = id_ast->children[0]->range_left - id_ast->children[0]->range_right + 1; this_width = id_ast->children[0]->range_left - id_ast->children[0]->range_right + 1;
} else } else
log_error("Failed to detect width for identifier %s at %s:%d!\n", str.c_str(), filename.c_str(), linenum); log_file_error(filename, linenum, "Failed to detect width for identifier %s!\n", str.c_str());
if (range) { if (range) {
if (range->children.size() == 1) if (range->children.size() == 1)
this_width = 1; this_width = 1;
@ -648,8 +648,8 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
while (left_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { } while (left_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
while (right_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { } while (right_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT) if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT)
log_error("Unsupported expression on dynamic range select on signal `%s' at %s:%d!\n", log_file_error(filename, linenum, "Unsupported expression on dynamic range select on signal `%s'!\n",
str.c_str(), filename.c_str(), linenum); str.c_str());
this_width = left_at_zero_ast->integer - right_at_zero_ast->integer + 1; this_width = left_at_zero_ast->integer - right_at_zero_ast->integer + 1;
delete left_at_zero_ast; delete left_at_zero_ast;
delete right_at_zero_ast; delete right_at_zero_ast;
@ -665,7 +665,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
case AST_TO_BITS: case AST_TO_BITS:
while (children[0]->simplify(true, false, false, 1, -1, false, false) == true) { } while (children[0]->simplify(true, false, false, 1, -1, false, false) == true) { }
if (children[0]->type != AST_CONSTANT) if (children[0]->type != AST_CONSTANT)
log_error("Left operand of tobits expression is not constant at %s:%d!\n", filename.c_str(), linenum); log_file_error(filename, linenum, "Left operand of tobits expression is not constant!\n");
children[1]->detectSignWidthWorker(sub_width_hint, sign_hint); children[1]->detectSignWidthWorker(sub_width_hint, sign_hint);
width_hint = max(width_hint, children[0]->bitsAsConst().as_int()); width_hint = max(width_hint, children[0]->bitsAsConst().as_int());
break; break;
@ -693,7 +693,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
case AST_REPLICATE: case AST_REPLICATE:
while (children[0]->simplify(true, false, false, 1, -1, false, true) == true) { } while (children[0]->simplify(true, false, false, 1, -1, false, true) == true) { }
if (children[0]->type != AST_CONSTANT) if (children[0]->type != AST_CONSTANT)
log_error("Left operand of replicate expression is not constant at %s:%d!\n", filename.c_str(), linenum); log_file_error(filename, linenum, "Left operand of replicate expression is not constant!\n");
children[1]->detectSignWidthWorker(sub_width_hint, sub_sign_hint); children[1]->detectSignWidthWorker(sub_width_hint, sub_sign_hint);
width_hint = max(width_hint, children[0]->bitsAsConst().as_int() * sub_width_hint); width_hint = max(width_hint, children[0]->bitsAsConst().as_int() * sub_width_hint);
sign_hint = false; sign_hint = false;
@ -767,7 +767,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
if (!id2ast->is_signed) if (!id2ast->is_signed)
sign_hint = false; sign_hint = false;
if (!id2ast->children[0]->range_valid) if (!id2ast->children[0]->range_valid)
log_error("Failed to detect width of memory access `%s' at %s:%d!\n", str.c_str(), filename.c_str(), linenum); log_file_error(filename, linenum, "Failed to detect width of memory access `%s'!\n", str.c_str());
this_width = id2ast->children[0]->range_left - id2ast->children[0]->range_right + 1; this_width = id2ast->children[0]->range_left - id2ast->children[0]->range_right + 1;
width_hint = max(width_hint, this_width); width_hint = max(width_hint, this_width);
break; break;
@ -777,8 +777,8 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
if (GetSize(children) == 1) { if (GetSize(children) == 1) {
while (children[0]->simplify(true, false, false, 1, -1, false, true) == true) { } while (children[0]->simplify(true, false, false, 1, -1, false, true) == true) { }
if (children[0]->type != AST_CONSTANT) if (children[0]->type != AST_CONSTANT)
log_error("System function %s called with non-const argument at %s:%d!\n", log_file_error(filename, linenum, "System function %s called with non-const argument!\n",
RTLIL::unescape_id(str).c_str(), filename.c_str(), linenum); RTLIL::unescape_id(str).c_str());
width_hint = max(width_hint, int(children[0]->asInt(true))); width_hint = max(width_hint, int(children[0]->asInt(true)));
} }
break; break;
@ -799,8 +799,8 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
default: default:
for (auto f : log_files) for (auto f : log_files)
current_ast->dumpAst(f, "verilog-ast> "); current_ast->dumpAst(f, "verilog-ast> ");
log_error("Don't know how to detect sign and width for %s node at %s:%d!\n", log_file_error(filename, linenum, "Don't know how to detect sign and width for %s node!\n",
type2str(type).c_str(), filename.c_str(), linenum); type2str(type).c_str());
} }
if (*found_real) if (*found_real)
@ -863,11 +863,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
// create an RTLIL::Wire for an AST_WIRE node // create an RTLIL::Wire for an AST_WIRE node
case AST_WIRE: { case AST_WIRE: {
if (current_module->wires_.count(str) != 0) if (current_module->wires_.count(str) != 0)
log_error("Re-definition of signal `%s' at %s:%d!\n", log_file_error(filename, linenum, "Re-definition of signal `%s'!\n",
str.c_str(), filename.c_str(), linenum); str.c_str());
if (!range_valid) if (!range_valid)
log_error("Signal `%s' with non-constant width at %s:%d!\n", log_file_error(filename, linenum, "Signal `%s' with non-constant width!\n",
str.c_str(), filename.c_str(), linenum); str.c_str());
log_assert(range_left >= range_right || (range_left == -1 && range_right == 0)); log_assert(range_left >= range_right || (range_left == -1 && range_right == 0));
@ -881,8 +881,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
for (auto &attr : attributes) { for (auto &attr : attributes) {
if (attr.second->type != AST_CONSTANT) if (attr.second->type != AST_CONSTANT)
log_error("Attribute `%s' with non-constant value at %s:%d!\n", log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n",
attr.first.c_str(), filename.c_str(), linenum); attr.first.c_str());
wire->attributes[attr.first] = attr.second->asAttrConst(); wire->attributes[attr.first] = attr.second->asAttrConst();
} }
} }
@ -891,16 +891,16 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
// create an RTLIL::Memory for an AST_MEMORY node // create an RTLIL::Memory for an AST_MEMORY node
case AST_MEMORY: { case AST_MEMORY: {
if (current_module->memories.count(str) != 0) if (current_module->memories.count(str) != 0)
log_error("Re-definition of memory `%s' at %s:%d!\n", log_file_error(filename, linenum, "Re-definition of memory `%s'!\n",
str.c_str(), filename.c_str(), linenum); str.c_str());
log_assert(children.size() >= 2); log_assert(children.size() >= 2);
log_assert(children[0]->type == AST_RANGE); log_assert(children[0]->type == AST_RANGE);
log_assert(children[1]->type == AST_RANGE); log_assert(children[1]->type == AST_RANGE);
if (!children[0]->range_valid || !children[1]->range_valid) if (!children[0]->range_valid || !children[1]->range_valid)
log_error("Memory `%s' with non-constant width or size at %s:%d!\n", log_file_error(filename, linenum, "Memory `%s' with non-constant width or size!\n",
str.c_str(), filename.c_str(), linenum); str.c_str());
RTLIL::Memory *memory = new RTLIL::Memory; RTLIL::Memory *memory = new RTLIL::Memory;
memory->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum); memory->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
@ -917,8 +917,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
for (auto &attr : attributes) { for (auto &attr : attributes) {
if (attr.second->type != AST_CONSTANT) if (attr.second->type != AST_CONSTANT)
log_error("Attribute `%s' with non-constant value at %s:%d!\n", log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n",
attr.first.c_str(), filename.c_str(), linenum); attr.first.c_str());
memory->attributes[attr.first] = attr.second->asAttrConst(); memory->attributes[attr.first] = attr.second->asAttrConst();
} }
} }
@ -937,8 +937,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
case AST_REALVALUE: case AST_REALVALUE:
{ {
RTLIL::SigSpec sig = realAsConst(width_hint); RTLIL::SigSpec sig = realAsConst(width_hint);
log_warning("converting real value %e to binary %s at %s:%d.\n", log_file_warning(filename, linenum, "converting real value %e to binary %s.\n",
realvalue, log_signal(sig), filename.c_str(), linenum); realvalue, log_signal(sig));
return sig; return sig;
} }
@ -958,25 +958,25 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum); wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
wire->name = str; wire->name = str;
if (flag_autowire) if (flag_autowire)
log_warning("Identifier `%s' is implicitly declared at %s:%d.\n", str.c_str(), filename.c_str(), linenum); log_file_warning(filename, linenum, "Identifier `%s' is implicitly declared.\n", str.c_str());
else else
log_error("Identifier `%s' is implicitly declared at %s:%d and `default_nettype is set to none.\n", str.c_str(), filename.c_str(), linenum); log_file_error(filename, linenum, "Identifier `%s' is implicitly declared and `default_nettype is set to none.\n", str.c_str());
} }
else if (id2ast->type == AST_PARAMETER || id2ast->type == AST_LOCALPARAM) { else if (id2ast->type == AST_PARAMETER || id2ast->type == AST_LOCALPARAM) {
if (id2ast->children[0]->type != AST_CONSTANT) if (id2ast->children[0]->type != AST_CONSTANT)
log_error("Parameter %s does not evaluate to constant value at %s:%d!\n", log_file_error(filename, linenum, "Parameter %s does not evaluate to constant value!\n",
str.c_str(), filename.c_str(), linenum); str.c_str());
chunk = RTLIL::Const(id2ast->children[0]->bits); chunk = RTLIL::Const(id2ast->children[0]->bits);
goto use_const_chunk; goto use_const_chunk;
} }
else if (!id2ast || (id2ast->type != AST_WIRE && id2ast->type != AST_AUTOWIRE && else if (!id2ast || (id2ast->type != AST_WIRE && id2ast->type != AST_AUTOWIRE &&
id2ast->type != AST_MEMORY) || current_module->wires_.count(str) == 0) id2ast->type != AST_MEMORY) || current_module->wires_.count(str) == 0)
log_error("Identifier `%s' doesn't map to any signal at %s:%d!\n", log_file_error(filename, linenum, "Identifier `%s' doesn't map to any signal!\n",
str.c_str(), filename.c_str(), linenum); str.c_str());
if (id2ast->type == AST_MEMORY) if (id2ast->type == AST_MEMORY)
log_error("Identifier `%s' does map to an unexpanded memory at %s:%d!\n", log_file_error(filename, linenum, "Identifier `%s' does map to an unexpanded memory!\n",
str.c_str(), filename.c_str(), linenum); str.c_str());
wire = current_module->wires_[str]; wire = current_module->wires_[str];
chunk.wire = wire; chunk.wire = wire;
@ -994,8 +994,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
while (left_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { } while (left_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
while (right_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { } while (right_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT) if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT)
log_error("Unsupported expression on dynamic range select on signal `%s' at %s:%d!\n", log_file_error(filename, linenum, "Unsupported expression on dynamic range select on signal `%s'!\n",
str.c_str(), filename.c_str(), linenum); str.c_str());
int width = left_at_zero_ast->integer - right_at_zero_ast->integer + 1; int width = left_at_zero_ast->integer - right_at_zero_ast->integer + 1;
AstNode *fake_ast = new AstNode(AST_NONE, clone(), children[0]->children.size() >= 2 ? AstNode *fake_ast = new AstNode(AST_NONE, clone(), children[0]->children.size() >= 2 ?
children[0]->children[1]->clone() : children[0]->children[0]->clone()); children[0]->children[1]->clone() : children[0]->children[0]->clone());
@ -1023,11 +1023,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
chunk.offset = (id2ast->range_left - id2ast->range_right + 1) - (chunk.offset + chunk.width); chunk.offset = (id2ast->range_left - id2ast->range_right + 1) - (chunk.offset + chunk.width);
if (chunk.offset >= source_width || chunk.offset + chunk.width < 0) { if (chunk.offset >= source_width || chunk.offset + chunk.width < 0) {
if (chunk.width == 1) if (chunk.width == 1)
log_warning("Range select out of bounds on signal `%s' at %s:%d: Setting result bit to undef.\n", log_file_warning(filename, linenum, "Range select out of bounds on signal `%s': Setting result bit to undef.\n",
str.c_str(), filename.c_str(), linenum); str.c_str());
else else
log_warning("Range select out of bounds on signal `%s' at %s:%d: Setting all %d result bits to undef.\n", log_file_warning(filename, linenum, "Range select out of bounds on signal `%s': Setting all %d result bits to undef.\n",
str.c_str(), filename.c_str(), linenum, chunk.width); str.c_str(), chunk.width);
chunk = RTLIL::SigChunk(RTLIL::State::Sx, chunk.width); chunk = RTLIL::SigChunk(RTLIL::State::Sx, chunk.width);
} else { } else {
if (chunk.width + chunk.offset > source_width) { if (chunk.width + chunk.offset > source_width) {
@ -1040,11 +1040,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
chunk.offset += add_undef_bits_lsb; chunk.offset += add_undef_bits_lsb;
} }
if (add_undef_bits_lsb) if (add_undef_bits_lsb)
log_warning("Range select out of bounds on signal `%s' at %s:%d: Setting %d LSB bits to undef.\n", log_file_warning(filename, linenum, "Range select out of bounds on signal `%s': Setting %d LSB bits to undef.\n",
str.c_str(), filename.c_str(), linenum, add_undef_bits_lsb); str.c_str(), add_undef_bits_lsb);
if (add_undef_bits_msb) if (add_undef_bits_msb)
log_warning("Range select out of bounds on signal `%s' at %s:%d: Setting %d MSB bits to undef.\n", log_file_warning(filename, linenum, "Range select out of bounds on signal `%s': Setting %d MSB bits to undef.\n",
str.c_str(), filename.c_str(), linenum, add_undef_bits_msb); str.c_str(), add_undef_bits_msb);
} }
} }
} }
@ -1083,7 +1083,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
RTLIL::SigSpec left = children[0]->genRTLIL(); RTLIL::SigSpec left = children[0]->genRTLIL();
RTLIL::SigSpec right = children[1]->genRTLIL(); RTLIL::SigSpec right = children[1]->genRTLIL();
if (!left.is_fully_const()) if (!left.is_fully_const())
log_error("Left operand of replicate expression is not constant at %s:%d!\n", filename.c_str(), linenum); log_file_error(filename, linenum, "Left operand of replicate expression is not constant!\n");
int count = left.as_int(); int count = left.as_int();
RTLIL::SigSpec sig; RTLIL::SigSpec sig;
for (int i = 0; i < count; i++) for (int i = 0; i < count; i++)
@ -1322,7 +1322,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
int num_words = 1; int num_words = 1;
if (type == AST_MEMINIT) { if (type == AST_MEMINIT) {
if (children[2]->type != AST_CONSTANT) if (children[2]->type != AST_CONSTANT)
log_error("Memory init with non-constant word count at %s:%d!\n", filename.c_str(), linenum); log_file_error(filename, linenum, "Memory init with non-constant word count!\n");
num_words = int(children[2]->asInt(false)); num_words = int(children[2]->asInt(false));
cell->parameters["\\WORDS"] = RTLIL::Const(num_words); cell->parameters["\\WORDS"] = RTLIL::Const(num_words);
} }
@ -1379,8 +1379,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
for (auto &attr : attributes) { for (auto &attr : attributes) {
if (attr.second->type != AST_CONSTANT) if (attr.second->type != AST_CONSTANT)
log_error("Attribute `%s' with non-constant value at %s:%d!\n", log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n",
attr.first.c_str(), filename.c_str(), linenum); attr.first.c_str());
cell->attributes[attr.first] = attr.second->asAttrConst(); cell->attributes[attr.first] = attr.second->asAttrConst();
} }
@ -1401,10 +1401,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
new_left.append(left[i]); new_left.append(left[i]);
new_right.append(right[i]); new_right.append(right[i]);
} }
log_warning("Ignoring assignment to constant bits at %s:%d:\n" log_file_warning(filename, linenum, "Ignoring assignment to constant bits:\n"
" old assignment: %s = %s\n new assignment: %s = %s.\n", " old assignment: %s = %s\n new assignment: %s = %s.\n",
filename.c_str(), linenum, log_signal(left), log_signal(right), log_signal(left), log_signal(right),
log_signal(new_left), log_signal(new_right)); log_signal(new_left), log_signal(new_right));
left = new_left; left = new_left;
right = new_right; right = new_right;
} }
@ -1418,8 +1418,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
int port_counter = 0, para_counter = 0; int port_counter = 0, para_counter = 0;
if (current_module->count_id(str) != 0) if (current_module->count_id(str) != 0)
log_error("Re-definition of cell `%s' at %s:%d!\n", log_file_error(filename, linenum, "Re-definition of cell `%s'!\n", str.c_str());
str.c_str(), filename.c_str(), linenum);
RTLIL::Cell *cell = current_module->addCell(str, ""); RTLIL::Cell *cell = current_module->addCell(str, "");
cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum); cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
@ -1435,16 +1434,15 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
if (child->type == AST_PARASET) { if (child->type == AST_PARASET) {
IdString paraname = child->str.empty() ? stringf("$%d", ++para_counter) : child->str; IdString paraname = child->str.empty() ? stringf("$%d", ++para_counter) : child->str;
if (child->children[0]->type == AST_REALVALUE) { if (child->children[0]->type == AST_REALVALUE) {
log_warning("Replacing floating point parameter %s.%s = %f with string at %s:%d.\n", log_file_warning(filename, linenum, "Replacing floating point parameter %s.%s = %f with string.\n",
log_id(cell), log_id(paraname), child->children[0]->realvalue, log_id(cell), log_id(paraname), child->children[0]->realvalue);
filename.c_str(), linenum);
auto strnode = AstNode::mkconst_str(stringf("%f", child->children[0]->realvalue)); auto strnode = AstNode::mkconst_str(stringf("%f", child->children[0]->realvalue));
strnode->cloneInto(child->children[0]); strnode->cloneInto(child->children[0]);
delete strnode; delete strnode;
} }
if (child->children[0]->type != AST_CONSTANT) if (child->children[0]->type != AST_CONSTANT)
log_error("Parameter %s.%s with non-constant value at %s:%d!\n", log_file_error(filename, linenum, "Parameter %s.%s with non-constant value!\n",
log_id(cell), log_id(paraname), filename.c_str(), linenum); log_id(cell), log_id(paraname));
cell->parameters[paraname] = child->children[0]->asParaConst(); cell->parameters[paraname] = child->children[0]->asParaConst();
continue; continue;
} }
@ -1465,8 +1463,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
} }
for (auto &attr : attributes) { for (auto &attr : attributes) {
if (attr.second->type != AST_CONSTANT) if (attr.second->type != AST_CONSTANT)
log_error("Attribute `%s' with non-constant value at %s:%d!\n", log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n",
attr.first.c_str(), filename.c_str(), linenum); attr.first.c_str());
cell->attributes[attr.first] = attr.second->asAttrConst(); cell->attributes[attr.first] = attr.second->asAttrConst();
} }
} }
@ -1493,19 +1491,19 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
int width = width_hint; int width = width_hint;
if (GetSize(children) > 1) if (GetSize(children) > 1)
log_error("System function %s got %d arguments, expected 1 or 0 at %s:%d.\n", log_file_error(filename, linenum, "System function %s got %d arguments, expected 1 or 0.\n",
RTLIL::unescape_id(str).c_str(), GetSize(children), filename.c_str(), linenum); RTLIL::unescape_id(str).c_str(), GetSize(children));
if (GetSize(children) == 1) { if (GetSize(children) == 1) {
if (children[0]->type != AST_CONSTANT) if (children[0]->type != AST_CONSTANT)
log_error("System function %s called with non-const argument at %s:%d!\n", log_file_error(filename, linenum, "System function %s called with non-const argument!\n",
RTLIL::unescape_id(str).c_str(), filename.c_str(), linenum); RTLIL::unescape_id(str).c_str());
width = children[0]->asInt(true); width = children[0]->asInt(true);
} }
if (width <= 0) if (width <= 0)
log_error("Failed to detect width of %s at %s:%d!\n", log_file_error(filename, linenum, "Failed to detect width of %s!\n",
RTLIL::unescape_id(str).c_str(), filename.c_str(), linenum); RTLIL::unescape_id(str).c_str());
Cell *cell = current_module->addCell(myid, str.substr(1)); Cell *cell = current_module->addCell(myid, str.substr(1));
cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum); cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
@ -1514,7 +1512,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
if (attributes.count("\\reg")) { if (attributes.count("\\reg")) {
auto &attr = attributes.at("\\reg"); auto &attr = attributes.at("\\reg");
if (attr->type != AST_CONSTANT) if (attr->type != AST_CONSTANT)
log_error("Attribute `reg' with non-constant value at %s:%d!\n", filename.c_str(), linenum); log_file_error(filename, linenum, "Attribute `reg' with non-constant value!\n");
cell->attributes["\\reg"] = attr->asAttrConst(); cell->attributes["\\reg"] = attr->asAttrConst();
} }
@ -1532,8 +1530,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
for (auto f : log_files) for (auto f : log_files)
current_ast->dumpAst(f, "verilog-ast> "); current_ast->dumpAst(f, "verilog-ast> ");
type_name = type2str(type); type_name = type2str(type);
log_error("Don't know how to generate RTLIL code for %s node at %s:%d!\n", log_file_error(filename, linenum, "Don't know how to generate RTLIL code for %s node!\n",
type_name.c_str(), filename.c_str(), linenum); type_name.c_str());
} }
return RTLIL::SigSpec(); return RTLIL::SigSpec();
@ -1563,4 +1561,3 @@ RTLIL::SigSpec AstNode::genWidthRTLIL(int width, const dict<RTLIL::SigBit, RTLIL
} }
YOSYS_NAMESPACE_END YOSYS_NAMESPACE_END

286
frontends/ast/simplify.cc
View File

@ -177,13 +177,13 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
// note that $display, $finish, and $stop are used for synthesis-time DRC so they're not in this list // note that $display, $finish, and $stop are used for synthesis-time DRC so they're not in this list
if ((type == AST_FCALL || type == AST_TCALL) && (str == "$strobe" || str == "$monitor" || str == "$time" || if ((type == AST_FCALL || type == AST_TCALL) && (str == "$strobe" || str == "$monitor" || str == "$time" ||
str == "$dumpfile" || str == "$dumpvars" || str == "$dumpon" || str == "$dumpoff" || str == "$dumpall")) { str == "$dumpfile" || str == "$dumpvars" || str == "$dumpon" || str == "$dumpoff" || str == "$dumpall")) {
log_warning("Ignoring call to system %s %s at %s:%d.\n", type == AST_FCALL ? "function" : "task", str.c_str(), filename.c_str(), linenum); log_file_warning(filename, linenum, "Ignoring call to system %s %s.\n", type == AST_FCALL ? "function" : "task", str.c_str());
delete_children(); delete_children();
str = std::string(); str = std::string();
} }
if ((type == AST_TCALL) && (str == "$display" || str == "$write") && (!current_always || current_always->type != AST_INITIAL)) { if ((type == AST_TCALL) && (str == "$display" || str == "$write") && (!current_always || current_always->type != AST_INITIAL)) {
log_warning("System task `%s' outside initial block is unsupported at %s:%d.\n", str.c_str(), filename.c_str(), linenum); log_file_warning(filename, linenum, "System task `%s' outside initial block is unsupported.\n", str.c_str());
delete_children(); delete_children();
str = std::string(); str = std::string();
} }
@ -195,14 +195,14 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
{ {
int nargs = GetSize(children); int nargs = GetSize(children);
if (nargs < 1) if (nargs < 1)
log_error("System task `%s' got %d arguments, expected >= 1 at %s:%d.\n", log_file_error(filename, linenum, "System task `%s' got %d arguments, expected >= 1.\n",
str.c_str(), int(children.size()), filename.c_str(), linenum); str.c_str(), int(children.size()));
// First argument is the format string // First argument is the format string
AstNode *node_string = children[0]; AstNode *node_string = children[0];
while (node_string->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } while (node_string->simplify(true, false, false, stage, width_hint, sign_hint, false)) { }
if (node_string->type != AST_CONSTANT) if (node_string->type != AST_CONSTANT)
log_error("Failed to evaluate system task `%s' with non-constant 1st argument at %s:%d.\n", str.c_str(), filename.c_str(), linenum); log_file_error(filename, linenum, "Failed to evaluate system task `%s' with non-constant 1st argument.\n", str.c_str());
std::string sformat = node_string->bitsAsConst().decode_string(); std::string sformat = node_string->bitsAsConst().decode_string();
// Other arguments are placeholders. Process the string as we go through it // Other arguments are placeholders. Process the string as we go through it
@ -215,7 +215,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
{ {
// If there's no next character, that's a problem // If there's no next character, that's a problem
if (i+1 >= sformat.length()) if (i+1 >= sformat.length())
log_error("System task `%s' called with `%%' at end of string at %s:%d.\n", str.c_str(), filename.c_str(), linenum); log_file_error(filename, linenum, "System task `%s' called with `%%' at end of string.\n", str.c_str());
char cformat = sformat[++i]; char cformat = sformat[++i];
@ -239,13 +239,13 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
case 'x': case 'x':
case 'X': case 'X':
if (next_arg >= GetSize(children)) if (next_arg >= GetSize(children))
log_error("Missing argument for %%%c format specifier in system task `%s' at %s:%d.\n", log_file_error(filename, linenum, "Missing argument for %%%c format specifier in system task `%s'.\n",
cformat, str.c_str(), filename.c_str(), linenum); cformat, str.c_str());
node_arg = children[next_arg++]; node_arg = children[next_arg++];
while (node_arg->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } while (node_arg->simplify(true, false, false, stage, width_hint, sign_hint, false)) { }
if (node_arg->type != AST_CONSTANT) if (node_arg->type != AST_CONSTANT)
log_error("Failed to evaluate system task `%s' with non-constant argument at %s:%d.\n", str.c_str(), filename.c_str(), linenum); log_file_error(filename, linenum, "Failed to evaluate system task `%s' with non-constant argument.\n", str.c_str());
break; break;
case 'm': case 'm':
@ -253,7 +253,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
break; break;
default: default:
log_error("System task `%s' called with invalid/unsupported format specifier at %s:%d.\n", str.c_str(), filename.c_str(), linenum); log_file_error(filename, linenum, "System task `%s' called with invalid/unsupported format specifier.\n", str.c_str());
break; break;
} }
@ -327,6 +327,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
if (node->type == AST_WIRE) { if (node->type == AST_WIRE) {
if (this_wire_scope.count(node->str) > 0) { if (this_wire_scope.count(node->str) > 0) {
AstNode *first_node = this_wire_scope[node->str]; AstNode *first_node = this_wire_scope[node->str];
if (first_node->is_input && node->is_reg)
goto wires_are_incompatible;
if (!node->is_input && !node->is_output && node->is_reg && node->children.size() == 0) if (!node->is_input && !node->is_output && node->is_reg && node->children.size() == 0)
goto wires_are_compatible; goto wires_are_compatible;
if (first_node->children.size() == 0 && node->children.size() == 1 && node->children[0]->type == AST_RANGE) { if (first_node->children.size() == 0 && node->children.size() == 1 && node->children[0]->type == AST_RANGE) {
@ -361,6 +363,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
first_node->is_output = true; first_node->is_output = true;
if (node->is_reg) if (node->is_reg)
first_node->is_reg = true; first_node->is_reg = true;
if (node->is_logic)
first_node->is_logic = true;
if (node->is_signed) if (node->is_signed)
first_node->is_signed = true; first_node->is_signed = true;
for (auto &it : node->attributes) { for (auto &it : node->attributes) {
@ -374,7 +378,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
continue; continue;
wires_are_incompatible: wires_are_incompatible:
if (stage > 1) if (stage > 1)
log_error("Incompatible re-declaration of wire %s at %s:%d.\n", node->str.c_str(), filename.c_str(), linenum); log_file_error(filename, linenum, "Incompatible re-declaration of wire %s.\n", node->str.c_str());
continue; continue;
} }
this_wire_scope[node->str] = node; this_wire_scope[node->str] = node;
@ -402,7 +406,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
if (type == AST_ALWAYS || type == AST_INITIAL) if (type == AST_ALWAYS || type == AST_INITIAL)
{ {
if (current_always != nullptr) if (current_always != nullptr)
log_error("Invalid nesting of always blocks and/or initializations at %s:%d.\n", filename.c_str(), linenum); log_file_error(filename, linenum, "Invalid nesting of always blocks and/or initializations.\n");
current_always = this; current_always = this;
current_always_clocked = false; current_always_clocked = false;
@ -440,6 +444,16 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
children[1]->detectSignWidth(width_hint, sign_hint); children[1]->detectSignWidth(width_hint, sign_hint);
width_hint = max(width_hint, backup_width_hint); width_hint = max(width_hint, backup_width_hint);
child_0_is_self_determined = true; child_0_is_self_determined = true;
// test only once, before optimizations and memory mappings but after assignment LHS was mapped to an identifier
if (children[0]->id2ast && !children[0]->was_checked) {
if ((type == AST_ASSIGN_LE || type == AST_ASSIGN_EQ) && children[0]->id2ast->is_logic)
children[0]->id2ast->is_reg = true; // if logic type is used in a block asignment
if ((type == AST_ASSIGN_LE || type == AST_ASSIGN_EQ) && !children[0]->id2ast->is_reg)
log_warning("wire '%s' is assigned in a block at %s:%d.\n", children[0]->str.c_str(), filename.c_str(), linenum);
if (type == AST_ASSIGN && children[0]->id2ast->is_reg)
log_warning("reg '%s' is assigned in a continuous assignment at %s:%d.\n", children[0]->str.c_str(), filename.c_str(), linenum);
children[0]->was_checked = true;
}
break; break;
case AST_PARAMETER: case AST_PARAMETER:
@ -451,7 +465,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
while (!children[1]->basic_prep && children[1]->simplify(false, false, false, stage, -1, false, true) == true) while (!children[1]->basic_prep && children[1]->simplify(false, false, false, stage, -1, false, true) == true)
did_something = true; did_something = true;
if (!children[1]->range_valid) if (!children[1]->range_valid)
log_error("Non-constant width range on parameter decl at %s:%d.\n", filename.c_str(), linenum); log_file_error(filename, linenum, "Non-constant width range on parameter decl.\n");
width_hint = max(width_hint, children[1]->range_left - children[1]->range_right + 1); width_hint = max(width_hint, children[1]->range_left - children[1]->range_right + 1);
} }
break; break;
@ -695,7 +709,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
if (type == AST_DEFPARAM && !children.empty()) if (type == AST_DEFPARAM && !children.empty())
{ {
if (children[0]->type != AST_IDENTIFIER) if (children[0]->type != AST_IDENTIFIER)
log_error("Module name in defparam at %s:%d contains non-constant expressions!\n", filename.c_str(), linenum); log_file_error(filename, linenum, "Module name in defparam contains non-constant expressions!\n");
string modname, paramname = children[0]->str; string modname, paramname = children[0]->str;
@ -712,13 +726,13 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
} }
if (pos == std::string::npos) if (pos == std::string::npos)
log_error("Can't find object for defparam `%s` at %s:%d!\n", RTLIL::unescape_id(paramname).c_str(), filename.c_str(), linenum); log_file_error(filename, linenum, "Can't find object for defparam `%s`!\n", RTLIL::unescape_id(paramname).c_str());
paramname = "\\" + paramname.substr(pos+1); paramname = "\\" + paramname.substr(pos+1);
if (current_scope.at(modname)->type != AST_CELL) if (current_scope.at(modname)->type != AST_CELL)
log_error("Defparam argument `%s . %s` does not match a cell at %s:%d!\n", log_file_error(filename, linenum, "Defparam argument `%s . %s` does not match a cell!\n",
RTLIL::unescape_id(modname).c_str(), RTLIL::unescape_id(paramname).c_str(), filename.c_str(), linenum); RTLIL::unescape_id(modname).c_str(), RTLIL::unescape_id(paramname).c_str());
AstNode *paraset = new AstNode(AST_PARASET, children[1]->clone(), GetSize(children) > 2 ? children[2]->clone() : NULL); AstNode *paraset = new AstNode(AST_PARASET, children[1]->clone(), GetSize(children) > 2 ? children[2]->clone() : NULL);
paraset->str = paramname; paraset->str = paramname;
@ -732,7 +746,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
if (type == AST_PREFIX) { if (type == AST_PREFIX) {
if (children[0]->type != AST_CONSTANT) { if (children[0]->type != AST_CONSTANT) {
// dumpAst(NULL, "> "); // dumpAst(NULL, "> ");
log_error("Index in generate block prefix syntax at %s:%d is not constant!\n", filename.c_str(), linenum); log_file_error(filename, linenum, "Index in generate block prefix syntax is not constant!\n");
} }
if (children[1]->type == AST_PREFIX) if (children[1]->type == AST_PREFIX)
children[1]->simplify(const_fold, at_zero, in_lvalue, stage, width_hint, sign_hint, in_param); children[1]->simplify(const_fold, at_zero, in_lvalue, stage, width_hint, sign_hint, in_param);
@ -748,9 +762,9 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
// evaluate TO_BITS nodes // evaluate TO_BITS nodes
if (type == AST_TO_BITS) { if (type == AST_TO_BITS) {
if (children[0]->type != AST_CONSTANT) if (children[0]->type != AST_CONSTANT)
log_error("Left operand of to_bits expression is not constant at %s:%d!\n", filename.c_str(), linenum); log_file_error(filename, linenum, "Left operand of to_bits expression is not constant!\n");
if (children[1]->type != AST_CONSTANT) if (children[1]->type != AST_CONSTANT)
log_error("Right operand of to_bits expression is not constant at %s:%d!\n", filename.c_str(), linenum); log_file_error(filename, linenum, "Right operand of to_bits expression is not constant!\n");
RTLIL::Const new_value = children[1]->bitsAsConst(children[0]->bitsAsConst().as_int(), children[1]->is_signed); RTLIL::Const new_value = children[1]->bitsAsConst(children[0]->bitsAsConst().as_int(), children[1]->is_signed);
newNode = mkconst_bits(new_value.bits, children[1]->is_signed); newNode = mkconst_bits(new_value.bits, children[1]->is_signed);
goto apply_newNode; goto apply_newNode;
@ -814,7 +828,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
multirange_dimensions.clear(); multirange_dimensions.clear();
for (auto range : children[1]->children) { for (auto range : children[1]->children) {
if (!range->range_valid) if (!range->range_valid)
log_error("Non-constant range on memory decl at %s:%d.\n", filename.c_str(), linenum); log_file_error(filename, linenum, "Non-constant range on memory decl.\n");
multirange_dimensions.push_back(min(range->range_left, range->range_right)); multirange_dimensions.push_back(min(range->range_left, range->range_right));
multirange_dimensions.push_back(max(range->range_left, range->range_right) - min(range->range_left, range->range_right) + 1); multirange_dimensions.push_back(max(range->range_left, range->range_right) - min(range->range_left, range->range_right) + 1);
total_size *= multirange_dimensions.back(); total_size *= multirange_dimensions.back();
@ -832,7 +846,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
for (int i = 0; 2*i < GetSize(id2ast->multirange_dimensions); i++) for (int i = 0; 2*i < GetSize(id2ast->multirange_dimensions); i++)
{ {
if (GetSize(children[0]->children) < i) if (GetSize(children[0]->children) < i)
log_error("Insufficient number of array indices for %s at %s:%d.\n", log_id(str), filename.c_str(), linenum); log_file_error(filename, linenum, "Insufficient number of array indices for %s.\n", log_id(str));
AstNode *new_index_expr = children[0]->children[i]->children.at(0)->clone(); AstNode *new_index_expr = children[0]->children[i]->children.at(0)->clone();
@ -861,12 +875,12 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
if (type == AST_PARAMETER || type == AST_LOCALPARAM) { if (type == AST_PARAMETER || type == AST_LOCALPARAM) {
if (children.size() > 1 && children[1]->type == AST_RANGE) { if (children.size() > 1 && children[1]->type == AST_RANGE) {
if (!children[1]->range_valid) if (!children[1]->range_valid)
log_error("Non-constant width range on parameter decl at %s:%d.\n", filename.c_str(), linenum); log_file_error(filename, linenum, "Non-constant width range on parameter decl.\n");
int width = std::abs(children[1]->range_left - children[1]->range_right) + 1; int width = std::abs(children[1]->range_left - children[1]->range_right) + 1;
if (children[0]->type == AST_REALVALUE) { if (children[0]->type == AST_REALVALUE) {
RTLIL::Const constvalue = children[0]->realAsConst(width); RTLIL::Const constvalue = children[0]->realAsConst(width);
log_warning("converting real value %e to binary %s at %s:%d.\n", log_file_warning(filename, linenum, "converting real value %e to binary %s.\n",
children[0]->realvalue, log_signal(constvalue), filename.c_str(), linenum); children[0]->realvalue, log_signal(constvalue));
delete children[0]; delete children[0];
children[0] = mkconst_bits(constvalue.bits, sign_hint); children[0] = mkconst_bits(constvalue.bits, sign_hint);
did_something = true; did_something = true;
@ -924,7 +938,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
if (type == AST_IDENTIFIER && children.size() == 2 && children[0]->type == AST_RANGE && children[1]->type == AST_RANGE && !in_lvalue) if (type == AST_IDENTIFIER && children.size() == 2 && children[0]->type == AST_RANGE && children[1]->type == AST_RANGE && !in_lvalue)
{ {
if (id2ast == NULL || id2ast->type != AST_MEMORY || children[0]->children.size() != 1) if (id2ast == NULL || id2ast->type != AST_MEMORY || children[0]->children.size() != 1)
log_error("Invalid bit-select on memory access at %s:%d!\n", filename.c_str(), linenum); log_file_error(filename, linenum, "Invalid bit-select on memory access!\n");
int mem_width, mem_size, addr_bits; int mem_width, mem_size, addr_bits;
id2ast->meminfo(mem_width, mem_size, addr_bits); id2ast->meminfo(mem_width, mem_size, addr_bits);
@ -949,6 +963,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
AstNode *assign = new AstNode(AST_ASSIGN_EQ, new AstNode(AST_IDENTIFIER), data); AstNode *assign = new AstNode(AST_ASSIGN_EQ, new AstNode(AST_IDENTIFIER), data);
assign->children[0]->str = wire_id; assign->children[0]->str = wire_id;
assign->children[0]->was_checked = true;
if (current_block) if (current_block)
{ {
@ -973,10 +988,10 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
} }
if (type == AST_WHILE) if (type == AST_WHILE)
log_error("While loops are only allowed in constant functions at %s:%d!\n", filename.c_str(), linenum); log_file_error(filename, linenum, "While loops are only allowed in constant functions!\n");
if (type == AST_REPEAT) if (type == AST_REPEAT)
log_error("Repeat loops are only allowed in constant functions at %s:%d!\n", filename.c_str(), linenum); log_file_error(filename, linenum, "Repeat loops are only allowed in constant functions!\n");
// unroll for loops and generate-for blocks // unroll for loops and generate-for blocks
if ((type == AST_GENFOR || type == AST_FOR) && children.size() != 0) if ((type == AST_GENFOR || type == AST_FOR) && children.size() != 0)
@ -991,31 +1006,31 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
body_ast = body_ast->children.at(0); body_ast = body_ast->children.at(0);
if (init_ast->type != AST_ASSIGN_EQ) if (init_ast->type != AST_ASSIGN_EQ)
log_error("Unsupported 1st expression of generate for-loop at %s:%d!\n", filename.c_str(), linenum); log_file_error(filename, linenum, "Unsupported 1st expression of generate for-loop!\n");
if (next_ast->type != AST_ASSIGN_EQ) if (next_ast->type != AST_ASSIGN_EQ)
log_error("Unsupported 3rd expression of generate for-loop at %s:%d!\n", filename.c_str(), linenum); log_file_error(filename, linenum, "Unsupported 3rd expression of generate for-loop!\n");
if (type == AST_GENFOR) { if (type == AST_GENFOR) {
if (init_ast->children[0]->id2ast == NULL || init_ast->children[0]->id2ast->type != AST_GENVAR) if (init_ast->children[0]->id2ast == NULL || init_ast->children[0]->id2ast->type != AST_GENVAR)
log_error("Left hand side of 1st expression of generate for-loop at %s:%d is not a gen var!\n", filename.c_str(), linenum); log_file_error(filename, linenum, "Left hand side of 1st expression of generate for-loop is not a gen var!\n");
if (next_ast->children[0]->id2ast == NULL || next_ast->children[0]->id2ast->type != AST_GENVAR) if (next_ast->children[0]->id2ast == NULL || next_ast->children[0]->id2ast->type != AST_GENVAR)
log_error("Left hand side of 3rd expression of generate for-loop at %s:%d is not a gen var!\n", filename.c_str(), linenum); log_file_error(filename, linenum, "Left hand side of 3rd expression of generate for-loop is not a gen var!\n");
} else { } else {
if (init_ast->children[0]->id2ast == NULL || init_ast->children[0]->id2ast->type != AST_WIRE) if (init_ast->children[0]->id2ast == NULL || init_ast->children[0]->id2ast->type != AST_WIRE)
log_error("Left hand side of 1st expression of generate for-loop at %s:%d is not a register!\n", filename.c_str(), linenum); log_file_error(filename, linenum, "Left hand side of 1st expression of generate for-loop is not a register!\n");
if (next_ast->children[0]->id2ast == NULL || next_ast->children[0]->id2ast->type != AST_WIRE) if (next_ast->children[0]->id2ast == NULL || next_ast->children[0]->id2ast->type != AST_WIRE)
log_error("Left hand side of 3rd expression of generate for-loop at %s:%d is not a register!\n", filename.c_str(), linenum); log_file_error(filename, linenum, "Left hand side of 3rd expression of generate for-loop is not a register!\n");
} }
if (init_ast->children[0]->id2ast != next_ast->children[0]->id2ast) if (init_ast->children[0]->id2ast != next_ast->children[0]->id2ast)
log_error("Incompatible left-hand sides in 1st and 3rd expression of generate for-loop at %s:%d!\n", filename.c_str(), linenum); log_file_error(filename, linenum, "Incompatible left-hand sides in 1st and 3rd expression of generate for-loop!\n");
// eval 1st expression // eval 1st expression
AstNode *varbuf = init_ast->children[1]->clone(); AstNode *varbuf = init_ast->children[1]->clone();
while (varbuf->simplify(true, false, false, stage, 32, true, false)) { } while (varbuf->simplify(true, false, false, stage, 32, true, false)) { }
if (varbuf->type != AST_CONSTANT) if (varbuf->type != AST_CONSTANT)
log_error("Right hand side of 1st expression of generate for-loop at %s:%d is not constant!\n", filename.c_str(), linenum); log_file_error(filename, linenum, "Right hand side of 1st expression of generate for-loop is not constant!\n");
varbuf = new AstNode(AST_LOCALPARAM, varbuf); varbuf = new AstNode(AST_LOCALPARAM, varbuf);
varbuf->str = init_ast->children[0]->str; varbuf->str = init_ast->children[0]->str;
@ -1037,7 +1052,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
while (buf->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } while (buf->simplify(true, false, false, stage, width_hint, sign_hint, false)) { }
if (buf->type != AST_CONSTANT) if (buf->type != AST_CONSTANT)
log_error("2nd expression of generate for-loop at %s:%d is not constant!\n", filename.c_str(), linenum); log_file_error(filename, linenum, "2nd expression of generate for-loop is not constant!\n");
if (buf->integer == 0) { if (buf->integer == 0) {
delete buf; delete buf;
@ -1078,7 +1093,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
while (buf->simplify(true, false, false, stage, 32, true, false)) { } while (buf->simplify(true, false, false, stage, 32, true, false)) { }
if (buf->type != AST_CONSTANT) if (buf->type != AST_CONSTANT)
log_error("Right hand side of 3rd expression of generate for-loop at %s:%d is not constant!\n", filename.c_str(), linenum); log_file_error(filename, linenum, "Right hand side of 3rd expression of generate for-loop is not constant!\n");
delete varbuf->children[0]; delete varbuf->children[0];
varbuf->children[0] = buf; varbuf->children[0] = buf;
@ -1095,8 +1110,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
{ {
for (size_t i = 0; i < children.size(); i++) for (size_t i = 0; i < children.size(); i++)
if (children[i]->type == AST_WIRE || children[i]->type == AST_MEMORY || children[i]->type == AST_PARAMETER || children[i]->type == AST_LOCALPARAM) if (children[i]->type == AST_WIRE || children[i]->type == AST_MEMORY || children[i]->type == AST_PARAMETER || children[i]->type == AST_LOCALPARAM)
log_error("Local declaration in unnamed block at %s:%d is an unsupported SystemVerilog feature!\n", log_file_error(children[i]->filename, children[i]->linenum, "Local declaration in unnamed block is an unsupported SystemVerilog feature!\n");
children[i]->filename.c_str(), children[i]->linenum);
} }
// transform block with name // transform block with name
@ -1144,7 +1158,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
if (buf->type != AST_CONSTANT) { if (buf->type != AST_CONSTANT) {
// for (auto f : log_files) // for (auto f : log_files)
// dumpAst(f, "verilog-ast> "); // dumpAst(f, "verilog-ast> ");
log_error("Condition for generate if at %s:%d is not constant!\n", filename.c_str(), linenum); log_file_error(filename, linenum, "Condition for generate if is not constant!\n");
} }
if (buf->asBool() != 0) { if (buf->asBool() != 0) {
delete buf; delete buf;
@ -1185,7 +1199,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
if (buf->type != AST_CONSTANT) { if (buf->type != AST_CONSTANT) {
// for (auto f : log_files) // for (auto f : log_files)
// dumpAst(f, "verilog-ast> "); // dumpAst(f, "verilog-ast> ");
log_error("Condition for generate case at %s:%d is not constant!\n", filename.c_str(), linenum); log_file_error(filename, linenum, "Condition for generate case is not constant!\n");
} }
bool ref_signed = buf->is_signed; bool ref_signed = buf->is_signed;
@ -1219,7 +1233,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
if (buf->type != AST_CONSTANT) { if (buf->type != AST_CONSTANT) {
// for (auto f : log_files) // for (auto f : log_files)
// dumpAst(f, "verilog-ast> "); // dumpAst(f, "verilog-ast> ");
log_error("Expression in generate case at %s:%d is not constant!\n", filename.c_str(), linenum); log_file_error(filename, linenum, "Expression in generate case is not constant!\n");
} }
bool is_selected = RTLIL::const_eq(ref_value, buf->bitsAsConst(), ref_signed && buf->is_signed, ref_signed && buf->is_signed, 1).as_bool(); bool is_selected = RTLIL::const_eq(ref_value, buf->bitsAsConst(), ref_signed && buf->is_signed, ref_signed && buf->is_signed, 1).as_bool();
@ -1260,7 +1274,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
if (type == AST_CELLARRAY) if (type == AST_CELLARRAY)
{ {
if (!children.at(0)->range_valid) if (!children.at(0)->range_valid)
log_error("Non-constant array range on cell array at %s:%d.\n", filename.c_str(), linenum); log_file_error(filename, linenum, "Non-constant array range on cell array.\n");
newNode = new AstNode(AST_GENBLOCK); newNode = new AstNode(AST_GENBLOCK);
int num = max(children.at(0)->range_left, children.at(0)->range_right) - min(children.at(0)->range_left, children.at(0)->range_right) + 1; int num = max(children.at(0)->range_left, children.at(0)->range_right) - min(children.at(0)->range_left, children.at(0)->range_right) + 1;
@ -1271,7 +1285,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
newNode->children.push_back(new_cell); newNode->children.push_back(new_cell);
new_cell->str += stringf("[%d]", idx); new_cell->str += stringf("[%d]", idx);
if (new_cell->type == AST_PRIMITIVE) { if (new_cell->type == AST_PRIMITIVE) {
log_error("Cell arrays of primitives are currently not supported at %s:%d.\n", filename.c_str(), linenum); log_file_error(filename, linenum, "Cell arrays of primitives are currently not supported.\n");
} else { } else {
log_assert(new_cell->children.at(0)->type == AST_CELLTYPE); log_assert(new_cell->children.at(0)->type == AST_CELLTYPE);
new_cell->children.at(0)->str = stringf("$array:%d:%d:%s", i, num, new_cell->children.at(0)->str.c_str()); new_cell->children.at(0)->str = stringf("$array:%d:%d:%s", i, num, new_cell->children.at(0)->str.c_str());
@ -1285,8 +1299,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
if (type == AST_PRIMITIVE) if (type == AST_PRIMITIVE)
{ {
if (children.size() < 2) if (children.size() < 2)
log_error("Insufficient number of arguments for primitive `%s' at %s:%d!\n", log_file_error(filename, linenum, "Insufficient number of arguments for primitive `%s'!\n",
str.c_str(), filename.c_str(), linenum); str.c_str());
std::vector<AstNode*> children_list; std::vector<AstNode*> children_list;
for (auto child : children) { for (auto child : children) {
@ -1301,8 +1315,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
if (str == "bufif0" || str == "bufif1" || str == "notif0" || str == "notif1") if (str == "bufif0" || str == "bufif1" || str == "notif0" || str == "notif1")
{ {
if (children_list.size() != 3) if (children_list.size() != 3)
log_error("Invalid number of arguments for primitive `%s' at %s:%d!\n", log_file_error(filename, linenum, "Invalid number of arguments for primitive `%s'!\n",
str.c_str(), filename.c_str(), linenum); str.c_str());
std::vector<RTLIL::State> z_const(1, RTLIL::State::Sz); std::vector<RTLIL::State> z_const(1, RTLIL::State::Sz);
@ -1387,8 +1401,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
while (left_at_zero_ast->simplify(true, true, false, stage, -1, false, false)) { } while (left_at_zero_ast->simplify(true, true, false, stage, -1, false, false)) { }
while (right_at_zero_ast->simplify(true, true, false, stage, -1, false, false)) { } while (right_at_zero_ast->simplify(true, true, false, stage, -1, false, false)) { }
if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT) if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT)
log_error("Unsupported expression on dynamic range select on signal `%s' at %s:%d!\n", log_file_error(filename, linenum, "Unsupported expression on dynamic range select on signal `%s'!\n",
str.c_str(), filename.c_str(), linenum); str.c_str());
result_width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1; result_width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1;
} }
did_something = true; did_something = true;
@ -1415,16 +1429,19 @@ skip_dynamic_range_lvalue_expansion:;
AstNode *wire_check = new AstNode(AST_WIRE); AstNode *wire_check = new AstNode(AST_WIRE);
wire_check->str = id_check; wire_check->str = id_check;
wire_check->was_checked = true;
current_ast_mod->children.push_back(wire_check); current_ast_mod->children.push_back(wire_check);
current_scope[wire_check->str] = wire_check; current_scope[wire_check->str] = wire_check;
while (wire_check->simplify(true, false, false, 1, -1, false, false)) { } while (wire_check->simplify(true, false, false, 1, -1, false, false)) { }
AstNode *wire_en = new AstNode(AST_WIRE); AstNode *wire_en = new AstNode(AST_WIRE);
wire_en->str = id_en; wire_en->str = id_en;
wire_en->was_checked = true;
current_ast_mod->children.push_back(wire_en); current_ast_mod->children.push_back(wire_en);
if (current_always_clocked) { if (current_always_clocked) {
current_ast_mod->children.push_back(new AstNode(AST_INITIAL, new AstNode(AST_BLOCK, new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), AstNode::mkconst_int(0, false, 1))))); current_ast_mod->children.push_back(new AstNode(AST_INITIAL, new AstNode(AST_BLOCK, new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), AstNode::mkconst_int(0, false, 1)))));
current_ast_mod->children.back()->children[0]->children[0]->children[0]->str = id_en; current_ast_mod->children.back()->children[0]->children[0]->children[0]->str = id_en;
current_ast_mod->children.back()->children[0]->children[0]->children[0]->was_checked = true;
} }
current_scope[wire_en->str] = wire_en; current_scope[wire_en->str] = wire_en;
while (wire_en->simplify(true, false, false, 1, -1, false, false)) { } while (wire_en->simplify(true, false, false, 1, -1, false, false)) { }
@ -1434,9 +1451,11 @@ skip_dynamic_range_lvalue_expansion:;
AstNode *assign_check = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_bits(x_bit, false)); AstNode *assign_check = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_bits(x_bit, false));
assign_check->children[0]->str = id_check; assign_check->children[0]->str = id_check;
assign_check->children[0]->was_checked = true;
AstNode *assign_en = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_int(0, false, 1)); AstNode *assign_en = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_int(0, false, 1));
assign_en->children[0]->str = id_en; assign_en->children[0]->str = id_en;
assign_en->children[0]->was_checked = true;
AstNode *default_signals = new AstNode(AST_BLOCK); AstNode *default_signals = new AstNode(AST_BLOCK);
default_signals->children.push_back(assign_check); default_signals->children.push_back(assign_check);
@ -1445,6 +1464,7 @@ skip_dynamic_range_lvalue_expansion:;
assign_check = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), new AstNode(AST_REDUCE_BOOL, children[0]->clone())); assign_check = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), new AstNode(AST_REDUCE_BOOL, children[0]->clone()));
assign_check->children[0]->str = id_check; assign_check->children[0]->str = id_check;
assign_check->children[0]->was_checked = true;
if (current_always == nullptr || current_always->type != AST_INITIAL) { if (current_always == nullptr || current_always->type != AST_INITIAL) {
assign_en = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_int(1, false, 1)); assign_en = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_int(1, false, 1));
@ -1453,6 +1473,7 @@ skip_dynamic_range_lvalue_expansion:;
assign_en->children[1]->str = "\\$initstate"; assign_en->children[1]->str = "\\$initstate";
} }
assign_en->children[0]->str = id_en; assign_en->children[0]->str = id_en;
assign_en->children[0]->was_checked = true;
newNode = new AstNode(AST_BLOCK); newNode = new AstNode(AST_BLOCK);
newNode->children.push_back(assign_check); newNode->children.push_back(assign_check);
@ -1561,12 +1582,14 @@ skip_dynamic_range_lvalue_expansion:;
AstNode *wire_addr = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(addr_bits-1, true), mkconst_int(0, true))); AstNode *wire_addr = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(addr_bits-1, true), mkconst_int(0, true)));
wire_addr->str = id_addr; wire_addr->str = id_addr;
wire_addr->was_checked = true;
current_ast_mod->children.push_back(wire_addr); current_ast_mod->children.push_back(wire_addr);
current_scope[wire_addr->str] = wire_addr; current_scope[wire_addr->str] = wire_addr;
while (wire_addr->simplify(true, false, false, 1, -1, false, false)) { } while (wire_addr->simplify(true, false, false, 1, -1, false, false)) { }
AstNode *wire_data = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(mem_width-1, true), mkconst_int(0, true))); AstNode *wire_data = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(mem_width-1, true), mkconst_int(0, true)));
wire_data->str = id_data; wire_data->str = id_data;
wire_data->was_checked = true;
wire_data->is_signed = mem_signed; wire_data->is_signed = mem_signed;
current_ast_mod->children.push_back(wire_data); current_ast_mod->children.push_back(wire_data);
current_scope[wire_data->str] = wire_data; current_scope[wire_data->str] = wire_data;
@ -1576,6 +1599,7 @@ skip_dynamic_range_lvalue_expansion:;
if (current_always->type != AST_INITIAL) { if (current_always->type != AST_INITIAL) {
wire_en = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(mem_width-1, true), mkconst_int(0, true))); wire_en = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(mem_width-1, true), mkconst_int(0, true)));
wire_en->str = id_en; wire_en->str = id_en;
wire_en->was_checked = true;
current_ast_mod->children.push_back(wire_en); current_ast_mod->children.push_back(wire_en);
current_scope[wire_en->str] = wire_en; current_scope[wire_en->str] = wire_en;
while (wire_en->simplify(true, false, false, 1, -1, false, false)) { } while (wire_en->simplify(true, false, false, 1, -1, false, false)) { }
@ -1591,14 +1615,17 @@ skip_dynamic_range_lvalue_expansion:;
AstNode *assign_addr = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_bits(x_bits_addr, false)); AstNode *assign_addr = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_bits(x_bits_addr, false));
assign_addr->children[0]->str = id_addr; assign_addr->children[0]->str = id_addr;
assign_addr->children[0]->was_checked = true;
AstNode *assign_data = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_bits(x_bits_data, false)); AstNode *assign_data = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_bits(x_bits_data, false));
assign_data->children[0]->str = id_data; assign_data->children[0]->str = id_data;
assign_data->children[0]->was_checked = true;
AstNode *assign_en = nullptr; AstNode *assign_en = nullptr;
if (current_always->type != AST_INITIAL) { if (current_always->type != AST_INITIAL) {
assign_en = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_int(0, false, mem_width)); assign_en = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_int(0, false, mem_width));
assign_en->children[0]->str = id_en; assign_en->children[0]->str = id_en;
assign_en->children[0]->was_checked = true;
} }
AstNode *default_signals = new AstNode(AST_BLOCK); AstNode *default_signals = new AstNode(AST_BLOCK);
@ -1610,6 +1637,7 @@ skip_dynamic_range_lvalue_expansion:;
assign_addr = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), children[0]->children[0]->children[0]->clone()); assign_addr = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), children[0]->children[0]->children[0]->clone());
assign_addr->children[0]->str = id_addr; assign_addr->children[0]->str = id_addr;
assign_addr->children[0]->was_checked = true;
if (children[0]->children.size() == 2) if (children[0]->children.size() == 2)
{ {
@ -1624,12 +1652,14 @@ skip_dynamic_range_lvalue_expansion:;
assign_data = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), assign_data = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER),
new AstNode(AST_CONCAT, mkconst_bits(padding_x, false), children[1]->clone())); new AstNode(AST_CONCAT, mkconst_bits(padding_x, false), children[1]->clone()));
assign_data->children[0]->str = id_data; assign_data->children[0]->str = id_data;
assign_data->children[0]->was_checked = true;
if (current_always->type != AST_INITIAL) { if (current_always->type != AST_INITIAL) {
for (int i = 0; i < mem_width; i++) for (int i = 0; i < mem_width; i++)
set_bits_en[i] = offset <= i && i < offset+width ? RTLIL::State::S1 : RTLIL::State::S0; set_bits_en[i] = offset <= i && i < offset+width ? RTLIL::State::S1 : RTLIL::State::S0;
assign_en = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_bits(set_bits_en, false)); assign_en = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_bits(set_bits_en, false));
assign_en->children[0]->str = id_en; assign_en->children[0]->str = id_en;
assign_en->children[0]->was_checked = true;
} }
} }
else else
@ -1645,12 +1675,13 @@ skip_dynamic_range_lvalue_expansion:;
while (left_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { } while (left_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
while (right_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { } while (right_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT) if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT)
log_error("Unsupported expression on dynamic range select on signal `%s' at %s:%d!\n", str.c_str(), filename.c_str(), linenum); log_file_error(filename, linenum, "Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str());
int width = left_at_zero_ast->integer - right_at_zero_ast->integer + 1; int width = left_at_zero_ast->integer - right_at_zero_ast->integer + 1;
assign_data = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), assign_data = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER),
new AstNode(AST_SHIFT_LEFT, children[1]->clone(), offset_ast->clone())); new AstNode(AST_SHIFT_LEFT, children[1]->clone(), offset_ast->clone()));
assign_data->children[0]->str = id_data; assign_data->children[0]->str = id_data;
assign_data->children[0]->was_checked = true;
if (current_always->type != AST_INITIAL) { if (current_always->type != AST_INITIAL) {
for (int i = 0; i < mem_width; i++) for (int i = 0; i < mem_width; i++)
@ -1658,6 +1689,7 @@ skip_dynamic_range_lvalue_expansion:;
assign_en = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), assign_en = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER),
new AstNode(AST_SHIFT_LEFT, mkconst_bits(set_bits_en, false), offset_ast->clone())); new AstNode(AST_SHIFT_LEFT, mkconst_bits(set_bits_en, false), offset_ast->clone()));
assign_en->children[0]->str = id_en; assign_en->children[0]->str = id_en;
assign_en->children[0]->was_checked = true;
} }
delete left_at_zero_ast; delete left_at_zero_ast;
@ -1669,10 +1701,12 @@ skip_dynamic_range_lvalue_expansion:;
{ {
assign_data = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), children[1]->clone()); assign_data = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), children[1]->clone());
assign_data->children[0]->str = id_data; assign_data->children[0]->str = id_data;
assign_data->children[0]->was_checked = true;
if (current_always->type != AST_INITIAL) { if (current_always->type != AST_INITIAL) {
assign_en = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_bits(set_bits_en, false)); assign_en = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_bits(set_bits_en, false));
assign_en->children[0]->str = id_en; assign_en->children[0]->str = id_en;
assign_en->children[0]->was_checked = true;
} }
} }
@ -1737,19 +1771,19 @@ skip_dynamic_range_lvalue_expansion:;
int num_steps = 1; int num_steps = 1;
if (GetSize(children) != 1 && GetSize(children) != 2) if (GetSize(children) != 1 && GetSize(children) != 2)
log_error("System function %s got %d arguments, expected 1 or 2 at %s:%d.\n", log_file_error(filename, linenum, "System function %s got %d arguments, expected 1 or 2.\n",
RTLIL::unescape_id(str).c_str(), int(children.size()), filename.c_str(), linenum); RTLIL::unescape_id(str).c_str(), int(children.size()));
if (!current_always_clocked) if (!current_always_clocked)
log_error("System function %s is only allowed in clocked blocks at %s:%d.\n", log_file_error(filename, linenum, "System function %s is only allowed in clocked blocks.\n",
RTLIL::unescape_id(str).c_str(), filename.c_str(), linenum); RTLIL::unescape_id(str).c_str());
if (GetSize(children) == 2) if (GetSize(children) == 2)
{ {
AstNode *buf = children[1]->clone(); AstNode *buf = children[1]->clone();
while (buf->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } while (buf->simplify(true, false, false, stage, width_hint, sign_hint, false)) { }
if (buf->type != AST_CONSTANT) if (buf->type != AST_CONSTANT)
log_error("Failed to evaluate system function `%s' with non-constant value at %s:%d.\n", str.c_str(), filename.c_str(), linenum); log_file_error(filename, linenum, "Failed to evaluate system function `%s' with non-constant value.\n", str.c_str());
num_steps = buf->asInt(true); num_steps = buf->asInt(true);
delete buf; delete buf;
@ -1805,12 +1839,12 @@ skip_dynamic_range_lvalue_expansion:;
if (str == "\\$stable" || str == "\\$rose" || str == "\\$fell") if (str == "\\$stable" || str == "\\$rose" || str == "\\$fell")
{ {
if (GetSize(children) != 1) if (GetSize(children) != 1)
log_error("System function %s got %d arguments, expected 1 at %s:%d.\n", log_file_error(filename, linenum, "System function %s got %d arguments, expected 1.\n",
RTLIL::unescape_id(str).c_str(), int(children.size()), filename.c_str(), linenum); RTLIL::unescape_id(str).c_str(), int(children.size()));
if (!current_always_clocked) if (!current_always_clocked)
log_error("System function %s is only allowed in clocked blocks at %s:%d.\n", log_file_error(filename, linenum, "System function %s is only allowed in clocked blocks.\n",
RTLIL::unescape_id(str).c_str(), filename.c_str(), linenum); RTLIL::unescape_id(str).c_str());
AstNode *present = children.at(0)->clone(); AstNode *present = children.at(0)->clone();
AstNode *past = clone(); AstNode *past = clone();
@ -1840,13 +1874,13 @@ skip_dynamic_range_lvalue_expansion:;
if (str == "\\$clog2") if (str == "\\$clog2")
{ {
if (children.size() != 1) if (children.size() != 1)
log_error("System function %s got %d arguments, expected 1 at %s:%d.\n", log_file_error(filename, linenum, "System function %s got %d arguments, expected 1.\n",
RTLIL::unescape_id(str).c_str(), int(children.size()), filename.c_str(), linenum); RTLIL::unescape_id(str).c_str(), int(children.size()));
AstNode *buf = children[0]->clone(); AstNode *buf = children[0]->clone();
while (buf->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } while (buf->simplify(true, false, false, stage, width_hint, sign_hint, false)) { }
if (buf->type != AST_CONSTANT) if (buf->type != AST_CONSTANT)
log_error("Failed to evaluate system function `%s' with non-constant value at %s:%d.\n", str.c_str(), filename.c_str(), linenum); log_file_error(filename, linenum, "Failed to evaluate system function `%s' with non-constant value.\n", str.c_str());
RTLIL::Const arg_value = buf->bitsAsConst(); RTLIL::Const arg_value = buf->bitsAsConst();
if (arg_value.as_bool()) if (arg_value.as_bool())
@ -1865,12 +1899,12 @@ skip_dynamic_range_lvalue_expansion:;
if (str == "\\$size" || str == "\\$bits") if (str == "\\$size" || str == "\\$bits")
{ {
if (str == "\\$bits" && children.size() != 1) if (str == "\\$bits" && children.size() != 1)
log_error("System function %s got %d arguments, expected 1 at %s:%d.\n", log_file_error(filename, linenum, "System function %s got %d arguments, expected 1.\n",
RTLIL::unescape_id(str).c_str(), int(children.size()), filename.c_str(), linenum); RTLIL::unescape_id(str).c_str(), int(children.size()));
if (str == "\\$size" && children.size() != 1 && children.size() != 2) if (str == "\\$size" && children.size() != 1 && children.size() != 2)
log_error("System function %s got %d arguments, expected 1 or 2 at %s:%d.\n", log_file_error(filename, linenum, "System function %s got %d arguments, expected 1 or 2.\n",
RTLIL::unescape_id(str).c_str(), int(children.size()), filename.c_str(), linenum); RTLIL::unescape_id(str).c_str(), int(children.size()));
int dim = 1; int dim = 1;
if (str == "\\$size" && children.size() == 2) { if (str == "\\$size" && children.size() == 2) {
@ -1893,7 +1927,7 @@ skip_dynamic_range_lvalue_expansion:;
if (id_ast == NULL && current_scope.count(buf->str)) if (id_ast == NULL && current_scope.count(buf->str))
id_ast = current_scope.at(buf->str); id_ast = current_scope.at(buf->str);
if (!id_ast) if (!id_ast)
log_error("Failed to resolve identifier %s for width detection at %s:%d!\n", buf->str.c_str(), filename.c_str(), linenum); log_file_error(filename, linenum, "Failed to resolve identifier %s for width detection!\n", buf->str.c_str());
if (id_ast->type == AST_MEMORY) { if (id_ast->type == AST_MEMORY) {
// We got here only if the argument is a memory // We got here only if the argument is a memory
// Otherwise $size() and $bits() return the expression width // Otherwise $size() and $bits() return the expression width
@ -1901,15 +1935,15 @@ skip_dynamic_range_lvalue_expansion:;
if (str == "\\$bits") { if (str == "\\$bits") {
if (mem_range->type == AST_RANGE) { if (mem_range->type == AST_RANGE) {
if (!mem_range->range_valid) if (!mem_range->range_valid)
log_error("Failed to detect width of memory access `%s' at %s:%d!\n", buf->str.c_str(), filename.c_str(), linenum); log_file_error(filename, linenum, "Failed to detect width of memory access `%s'!\n", buf->str.c_str());
mem_depth = mem_range->range_left - mem_range->range_right + 1; mem_depth = mem_range->range_left - mem_range->range_right + 1;
} else } else
log_error("Unknown memory depth AST type in `%s' at %s:%d!\n", buf->str.c_str(), filename.c_str(), linenum); log_file_error(filename, linenum, "Unknown memory depth AST type in `%s'!\n", buf->str.c_str());
} else { } else {
// $size() // $size()
if (mem_range->type == AST_RANGE) { if (mem_range->type == AST_RANGE) {
if (!mem_range->range_valid) if (!mem_range->range_valid)
log_error("Failed to detect width of memory access `%s' at %s:%d!\n", buf->str.c_str(), filename.c_str(), linenum); log_file_error(filename, linenum, "Failed to detect width of memory access `%s'!\n", buf->str.c_str());
int dims; int dims;
if (id_ast->multirange_dimensions.empty()) if (id_ast->multirange_dimensions.empty())
dims = 1; dims = 1;
@ -1920,9 +1954,9 @@ skip_dynamic_range_lvalue_expansion:;
else if (dim <= dims) { else if (dim <= dims) {
width_hint = id_ast->multirange_dimensions[2*dim-1]; width_hint = id_ast->multirange_dimensions[2*dim-1];
} else if ((dim > dims+1) || (dim < 0)) } else if ((dim > dims+1) || (dim < 0))
log_error("Dimension %d out of range in `%s', as it only has dimensions 1..%d at %s:%d!\n", dim, buf->str.c_str(), dims+1, filename.c_str(), linenum); log_file_error(filename, linenum, "Dimension %d out of range in `%s', as it only has dimensions 1..%d!\n", dim, buf->str.c_str(), dims+1);
} else } else
log_error("Unknown memory depth AST type in `%s' at %s:%d!\n", buf->str.c_str(), filename.c_str(), linenum); log_file_error(filename, linenum, "Unknown memory depth AST type in `%s'!\n", buf->str.c_str());
} }
} }
} }
@ -1943,19 +1977,19 @@ skip_dynamic_range_lvalue_expansion:;
if (func_with_two_arguments) { if (func_with_two_arguments) {
if (children.size() != 2) if (children.size() != 2)
log_error("System function %s got %d arguments, expected 2 at %s:%d.\n", log_file_error(filename, linenum, "System function %s got %d arguments, expected 2.\n",
RTLIL::unescape_id(str).c_str(), int(children.size()), filename.c_str(), linenum); RTLIL::unescape_id(str).c_str(), int(children.size()));
} else { } else {
if (children.size() != 1) if (children.size() != 1)
log_error("System function %s got %d arguments, expected 1 at %s:%d.\n", log_file_error(filename, linenum, "System function %s got %d arguments, expected 1.\n",
RTLIL::unescape_id(str).c_str(), int(children.size()), filename.c_str(), linenum); RTLIL::unescape_id(str).c_str(), int(children.size()));
} }
if (children.size() >= 1) { if (children.size() >= 1) {
while (children[0]->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } while (children[0]->simplify(true, false, false, stage, width_hint, sign_hint, false)) { }
if (!children[0]->isConst()) if (!children[0]->isConst())
log_error("Failed to evaluate system function `%s' with non-constant argument at %s:%d.\n", log_file_error(filename, linenum, "Failed to evaluate system function `%s' with non-constant argument.\n",
RTLIL::unescape_id(str).c_str(), filename.c_str(), linenum); RTLIL::unescape_id(str).c_str());
int child_width_hint = width_hint; int child_width_hint = width_hint;
bool child_sign_hint = sign_hint; bool child_sign_hint = sign_hint;
children[0]->detectSignWidth(child_width_hint, child_sign_hint); children[0]->detectSignWidth(child_width_hint, child_sign_hint);
@ -1965,8 +1999,8 @@ skip_dynamic_range_lvalue_expansion:;
if (children.size() >= 2) { if (children.size() >= 2) {
while (children[1]->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } while (children[1]->simplify(true, false, false, stage, width_hint, sign_hint, false)) { }
if (!children[1]->isConst()) if (!children[1]->isConst())
log_error("Failed to evaluate system function `%s' with non-constant argument at %s:%d.\n", log_file_error(filename, linenum, "Failed to evaluate system function `%s' with non-constant argument.\n",
RTLIL::unescape_id(str).c_str(), filename.c_str(), linenum); RTLIL::unescape_id(str).c_str());
int child_width_hint = width_hint; int child_width_hint = width_hint;
bool child_sign_hint = sign_hint; bool child_sign_hint = sign_hint;
children[1]->detectSignWidth(child_width_hint, child_sign_hint); children[1]->detectSignWidth(child_width_hint, child_sign_hint);
@ -2018,14 +2052,14 @@ skip_dynamic_range_lvalue_expansion:;
for (int i = 2; i < GetSize(dpi_decl->children); i++) for (int i = 2; i < GetSize(dpi_decl->children); i++)
{ {
if (i-2 >= GetSize(children)) if (i-2 >= GetSize(children))
log_error("Insufficient number of arguments in DPI function call at %s:%d.\n", filename.c_str(), linenum); log_file_error(filename, linenum, "Insufficient number of arguments in DPI function call.\n");
argtypes.push_back(RTLIL::unescape_id(dpi_decl->children.at(i)->str)); argtypes.push_back(RTLIL::unescape_id(dpi_decl->children.at(i)->str));
args.push_back(children.at(i-2)->clone()); args.push_back(children.at(i-2)->clone());
while (args.back()->simplify(true, false, false, stage, -1, false, true)) { } while (args.back()->simplify(true, false, false, stage, -1, false, true)) { }
if (args.back()->type != AST_CONSTANT && args.back()->type != AST_REALVALUE) if (args.back()->type != AST_CONSTANT && args.back()->type != AST_REALVALUE)
log_error("Failed to evaluate DPI function with non-constant argument at %s:%d.\n", filename.c_str(), linenum); log_file_error(filename, linenum, "Failed to evaluate DPI function with non-constant argument.\n");
} }
newNode = dpi_call(rtype, fname, argtypes, args); newNode = dpi_call(rtype, fname, argtypes, args);
@ -2037,7 +2071,7 @@ skip_dynamic_range_lvalue_expansion:;
} }
if (current_scope.count(str) == 0 || current_scope[str]->type != AST_FUNCTION) if (current_scope.count(str) == 0 || current_scope[str]->type != AST_FUNCTION)
log_error("Can't resolve function name `%s' at %s:%d.\n", str.c_str(), filename.c_str(), linenum); log_file_error(filename, linenum, "Can't resolve function name `%s'.\n", str.c_str());
} }
if (type == AST_TCALL) if (type == AST_TCALL)
@ -2045,26 +2079,26 @@ skip_dynamic_range_lvalue_expansion:;
if (str == "$finish" || str == "$stop") if (str == "$finish" || str == "$stop")
{ {
if (!current_always || current_always->type != AST_INITIAL) if (!current_always || current_always->type != AST_INITIAL)
log_error("System task `%s' outside initial block is unsupported at %s:%d.\n", str.c_str(), filename.c_str(), linenum); log_file_error(filename, linenum, "System task `%s' outside initial block is unsupported.\n", str.c_str());
log_error("System task `%s' executed at %s:%d.\n", str.c_str(), filename.c_str(), linenum); log_file_error(filename, linenum, "System task `%s' executed.\n", str.c_str());
} }
if (str == "\\$readmemh" || str == "\\$readmemb") if (str == "\\$readmemh" || str == "\\$readmemb")
{ {
if (GetSize(children) < 2 || GetSize(children) > 4) if (GetSize(children) < 2 || GetSize(children) > 4)
log_error("System function %s got %d arguments, expected 2-4 at %s:%d.\n", log_file_error(filename, linenum, "System function %s got %d arguments, expected 2-4.\n",
RTLIL::unescape_id(str).c_str(), int(children.size()), filename.c_str(), linenum); RTLIL::unescape_id(str).c_str(), int(children.size()));
AstNode *node_filename = children[0]->clone(); AstNode *node_filename = children[0]->clone();
while (node_filename->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } while (node_filename->simplify(true, false, false, stage, width_hint, sign_hint, false)) { }
if (node_filename->type != AST_CONSTANT) if (node_filename->type != AST_CONSTANT)
log_error("Failed to evaluate system function `%s' with non-constant 1st argument at %s:%d.\n", str.c_str(), filename.c_str(), linenum); log_file_error(filename, linenum, "Failed to evaluate system function `%s' with non-constant 1st argument.\n", str.c_str());
AstNode *node_memory = children[1]->clone(); AstNode *node_memory = children[1]->clone();
while (node_memory->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } while (node_memory->simplify(true, false, false, stage, width_hint, sign_hint, false)) { }
if (node_memory->type != AST_IDENTIFIER || node_memory->id2ast == nullptr || node_memory->id2ast->type != AST_MEMORY) if (node_memory->type != AST_IDENTIFIER || node_memory->id2ast == nullptr || node_memory->id2ast->type != AST_MEMORY)
log_error("Failed to evaluate system function `%s' with non-memory 2nd argument at %s:%d.\n", str.c_str(), filename.c_str(), linenum); log_file_error(filename, linenum, "Failed to evaluate system function `%s' with non-memory 2nd argument.\n", str.c_str());
int start_addr = -1, finish_addr = -1; int start_addr = -1, finish_addr = -1;
@ -2072,7 +2106,7 @@ skip_dynamic_range_lvalue_expansion:;
AstNode *node_addr = children[2]->clone(); AstNode *node_addr = children[2]->clone();
while (node_addr->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } while (node_addr->simplify(true, false, false, stage, width_hint, sign_hint, false)) { }
if (node_addr->type != AST_CONSTANT) if (node_addr->type != AST_CONSTANT)
log_error("Failed to evaluate system function `%s' with non-constant 3rd argument at %s:%d.\n", str.c_str(), filename.c_str(), linenum); log_file_error(filename, linenum, "Failed to evaluate system function `%s' with non-constant 3rd argument.\n", str.c_str());
start_addr = int(node_addr->asInt(false)); start_addr = int(node_addr->asInt(false));
} }
@ -2080,7 +2114,7 @@ skip_dynamic_range_lvalue_expansion:;
AstNode *node_addr = children[3]->clone(); AstNode *node_addr = children[3]->clone();
while (node_addr->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } while (node_addr->simplify(true, false, false, stage, width_hint, sign_hint, false)) { }
if (node_addr->type != AST_CONSTANT) if (node_addr->type != AST_CONSTANT)
log_error("Failed to evaluate system function `%s' with non-constant 4th argument at %s:%d.\n", str.c_str(), filename.c_str(), linenum); log_file_error(filename, linenum, "Failed to evaluate system function `%s' with non-constant 4th argument.\n", str.c_str());
finish_addr = int(node_addr->asInt(false)); finish_addr = int(node_addr->asInt(false));
} }
@ -2106,7 +2140,7 @@ skip_dynamic_range_lvalue_expansion:;
} }
if (current_scope.count(str) == 0 || current_scope[str]->type != AST_TASK) if (current_scope.count(str) == 0 || current_scope[str]->type != AST_TASK)
log_error("Can't resolve task name `%s' at %s:%d.\n", str.c_str(), filename.c_str(), linenum); log_file_error(filename, linenum, "Can't resolve task name `%s'.\n", str.c_str());
} }
AstNode *decl = current_scope[str]; AstNode *decl = current_scope[str];
@ -2134,9 +2168,9 @@ skip_dynamic_range_lvalue_expansion:;
} }
if (in_param) if (in_param)
log_error("Non-constant function call in constant expression at %s:%d.\n", filename.c_str(), linenum); log_file_error(filename, linenum, "Non-constant function call in constant expression.\n");
if (require_const_eval) if (require_const_eval)
log_error("Function %s can only be called with constant arguments at %s:%d.\n", str.c_str(), filename.c_str(), linenum); log_file_error(filename, linenum, "Function %s can only be called with constant arguments.\n", str.c_str());
} }
size_t arg_count = 0; size_t arg_count = 0;
@ -2253,7 +2287,7 @@ skip_dynamic_range_lvalue_expansion:;
goto tcall_incompatible_wires; goto tcall_incompatible_wires;
} else { } else {
tcall_incompatible_wires: tcall_incompatible_wires:
log_error("Incompatible re-declaration of wire %s at %s:%d.\n", child->str.c_str(), filename.c_str(), linenum); log_file_error(filename, linenum, "Incompatible re-declaration of wire %s.\n", child->str.c_str());
} }
} }
} }
@ -2641,7 +2675,7 @@ AstNode *AstNode::readmem(bool is_readmemh, std::string mem_filename, AstNode *m
yosys_input_files.insert(mem_filename); yosys_input_files.insert(mem_filename);
if (f.fail()) if (f.fail())
log_error("Can not open file `%s` for %s at %s:%d.\n", mem_filename.c_str(), str.c_str(), filename.c_str(), linenum); log_file_error(filename, linenum, "Can not open file `%s` for %s.\n", mem_filename.c_str(), str.c_str());
log_assert(GetSize(memory->children) == 2 && memory->children[1]->type == AST_RANGE && memory->children[1]->range_valid); log_assert(GetSize(memory->children) == 2 && memory->children[1]->type == AST_RANGE && memory->children[1]->range_valid);
int range_left = memory->children[1]->range_left, range_right = memory->children[1]->range_right; int range_left = memory->children[1]->range_left, range_right = memory->children[1]->range_right;
@ -2687,7 +2721,7 @@ AstNode *AstNode::readmem(bool is_readmemh, std::string mem_filename, AstNode *m
char *endptr; char *endptr;
cursor = strtol(nptr, &endptr, 16); cursor = strtol(nptr, &endptr, 16);
if (!*nptr || *endptr) if (!*nptr || *endptr)
log_error("Can not parse address `%s` for %s at %s:%d.\n", nptr, str.c_str(), filename.c_str(), linenum); log_file_error(filename, linenum, "Can not parse address `%s` for %s.\n", nptr, str.c_str());
continue; continue;
} }
@ -2943,7 +2977,7 @@ bool AstNode::mem2reg_check(pool<AstNode*> &mem2reg_set)
return false; return false;
if (children.empty() || children[0]->type != AST_RANGE || GetSize(children[0]->children) != 1) if (children.empty() || children[0]->type != AST_RANGE || GetSize(children[0]->children) != 1)
log_error("Invalid array access at %s:%d.\n", filename.c_str(), linenum); log_file_error(filename, linenum, "Invalid array access.\n");
return true; return true;
} }
@ -3008,6 +3042,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod,
AstNode *wire_addr = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(addr_bits-1, true), mkconst_int(0, true))); AstNode *wire_addr = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(addr_bits-1, true), mkconst_int(0, true)));
wire_addr->str = id_addr; wire_addr->str = id_addr;
wire_addr->is_reg = true; wire_addr->is_reg = true;
wire_addr->was_checked = true;
wire_addr->attributes["\\nosync"] = AstNode::mkconst_int(1, false); wire_addr->attributes["\\nosync"] = AstNode::mkconst_int(1, false);
mod->children.push_back(wire_addr); mod->children.push_back(wire_addr);
while (wire_addr->simplify(true, false, false, 1, -1, false, false)) { } while (wire_addr->simplify(true, false, false, 1, -1, false, false)) { }
@ -3015,6 +3050,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod,
AstNode *wire_data = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(mem_width-1, true), mkconst_int(0, true))); AstNode *wire_data = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(mem_width-1, true), mkconst_int(0, true)));
wire_data->str = id_data; wire_data->str = id_data;
wire_data->is_reg = true; wire_data->is_reg = true;
wire_data->was_checked = true;
wire_data->is_signed = mem_signed; wire_data->is_signed = mem_signed;
wire_data->attributes["\\nosync"] = AstNode::mkconst_int(1, false); wire_data->attributes["\\nosync"] = AstNode::mkconst_int(1, false);
mod->children.push_back(wire_data); mod->children.push_back(wire_data);
@ -3083,6 +3119,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod,
AstNode *wire_addr = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(addr_bits-1, true), mkconst_int(0, true))); AstNode *wire_addr = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(addr_bits-1, true), mkconst_int(0, true)));
wire_addr->str = id_addr; wire_addr->str = id_addr;
wire_addr->is_reg = true; wire_addr->is_reg = true;
wire_addr->was_checked = true;
if (block) if (block)
wire_addr->attributes["\\nosync"] = AstNode::mkconst_int(1, false); wire_addr->attributes["\\nosync"] = AstNode::mkconst_int(1, false);
mod->children.push_back(wire_addr); mod->children.push_back(wire_addr);
@ -3091,6 +3128,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod,
AstNode *wire_data = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(mem_width-1, true), mkconst_int(0, true))); AstNode *wire_data = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(mem_width-1, true), mkconst_int(0, true)));
wire_data->str = id_data; wire_data->str = id_data;
wire_data->is_reg = true; wire_data->is_reg = true;
wire_data->was_checked = true;
wire_data->is_signed = mem_signed; wire_data->is_signed = mem_signed;
if (block) if (block)
wire_data->attributes["\\nosync"] = AstNode::mkconst_int(1, false); wire_data->attributes["\\nosync"] = AstNode::mkconst_int(1, false);
@ -3099,6 +3137,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod,
AstNode *assign_addr = new AstNode(block ? AST_ASSIGN_EQ : AST_ASSIGN, new AstNode(AST_IDENTIFIER), children[0]->children[0]->clone()); AstNode *assign_addr = new AstNode(block ? AST_ASSIGN_EQ : AST_ASSIGN, new AstNode(AST_IDENTIFIER), children[0]->children[0]->clone());
assign_addr->children[0]->str = id_addr; assign_addr->children[0]->str = id_addr;
assign_addr->children[0]->was_checked = true;
AstNode *case_node = new AstNode(AST_CASE, new AstNode(AST_IDENTIFIER)); AstNode *case_node = new AstNode(AST_CASE, new AstNode(AST_IDENTIFIER));
case_node->children[0]->str = id_addr; case_node->children[0]->str = id_addr;
@ -3109,6 +3148,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod,
AstNode *cond_node = new AstNode(AST_COND, AstNode::mkconst_int(i, false, addr_bits), new AstNode(AST_BLOCK)); AstNode *cond_node = new AstNode(AST_COND, AstNode::mkconst_int(i, false, addr_bits), new AstNode(AST_BLOCK));
AstNode *assign_reg = new AstNode(AST_ASSIGN_EQ, new AstNode(AST_IDENTIFIER), new AstNode(AST_IDENTIFIER)); AstNode *assign_reg = new AstNode(AST_ASSIGN_EQ, new AstNode(AST_IDENTIFIER), new AstNode(AST_IDENTIFIER));
assign_reg->children[0]->str = id_data; assign_reg->children[0]->str = id_data;
assign_reg->children[0]->was_checked = true;
assign_reg->children[1]->str = stringf("%s[%d]", str.c_str(), i); assign_reg->children[1]->str = stringf("%s[%d]", str.c_str(), i);
cond_node->children[1]->children.push_back(assign_reg); cond_node->children[1]->children.push_back(assign_reg);
case_node->children.push_back(cond_node); case_node->children.push_back(cond_node);
@ -3121,6 +3161,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod,
AstNode *cond_node = new AstNode(AST_COND, new AstNode(AST_DEFAULT), new AstNode(AST_BLOCK)); AstNode *cond_node = new AstNode(AST_COND, new AstNode(AST_DEFAULT), new AstNode(AST_BLOCK));
AstNode *assign_reg = new AstNode(AST_ASSIGN_EQ, new AstNode(AST_IDENTIFIER), AstNode::mkconst_bits(x_bits, false)); AstNode *assign_reg = new AstNode(AST_ASSIGN_EQ, new AstNode(AST_IDENTIFIER), AstNode::mkconst_bits(x_bits, false));
assign_reg->children[0]->str = id_data; assign_reg->children[0]->str = id_data;
assign_reg->children[0]->was_checked = true;
cond_node->children[1]->children.push_back(assign_reg); cond_node->children[1]->children.push_back(assign_reg);
case_node->children.push_back(cond_node); case_node->children.push_back(cond_node);
@ -3202,13 +3243,13 @@ void AstNode::replace_variables(std::map<std::string, AstNode::varinfo_t> &varia
int offset = variables.at(str).offset, width = variables.at(str).val.bits.size(); int offset = variables.at(str).offset, width = variables.at(str).val.bits.size();
if (!children.empty()) { if (!children.empty()) {
if (children.size() != 1 || children.at(0)->type != AST_RANGE) if (children.size() != 1 || children.at(0)->type != AST_RANGE)
log_error("Memory access in constant function is not supported in %s:%d (called from %s:%d).\n", log_file_error(filename, linenum, "Memory access in constant function is not supported\n%s:%d: ...called from here.\n",
filename.c_str(), linenum, fcall->filename.c_str(), fcall->linenum); fcall->filename.c_str(), fcall->linenum);
children.at(0)->replace_variables(variables, fcall); children.at(0)->replace_variables(variables, fcall);
while (simplify(true, false, false, 1, -1, false, true)) { } while (simplify(true, false, false, 1, -1, false, true)) { }
if (!children.at(0)->range_valid) if (!children.at(0)->range_valid)
log_error("Non-constant range in %s:%d (called from %s:%d).\n", log_file_error(filename, linenum, "Non-constant range\n%s:%d: ... called from here.\n",
filename.c_str(), linenum, fcall->filename.c_str(), fcall->linenum); fcall->filename.c_str(), fcall->linenum);
offset = min(children.at(0)->range_left, children.at(0)->range_right); offset = min(children.at(0)->range_left, children.at(0)->range_right);
width = min(std::abs(children.at(0)->range_left - children.at(0)->range_right) + 1, width); width = min(std::abs(children.at(0)->range_left - children.at(0)->range_right) + 1, width);
} }
@ -3247,8 +3288,8 @@ AstNode *AstNode::eval_const_function(AstNode *fcall)
{ {
while (child->simplify(true, false, false, 1, -1, false, true)) { } while (child->simplify(true, false, false, 1, -1, false, true)) { }
if (!child->range_valid) if (!child->range_valid)
log_error("Can't determine size of variable %s in %s:%d (called from %s:%d).\n", log_file_error(child->filename, child->linenum, "Can't determine size of variable %s\n%s:%d: ... called from here.\n",
child->str.c_str(), child->filename.c_str(), child->linenum, fcall->filename.c_str(), fcall->linenum); child->str.c_str(), fcall->filename.c_str(), fcall->linenum);
variables[child->str].val = RTLIL::Const(RTLIL::State::Sx, abs(child->range_left - child->range_right)+1); variables[child->str].val = RTLIL::Const(RTLIL::State::Sx, abs(child->range_left - child->range_right)+1);
variables[child->str].offset = min(child->range_left, child->range_right); variables[child->str].offset = min(child->range_left, child->range_right);
variables[child->str].is_signed = child->is_signed; variables[child->str].is_signed = child->is_signed;
@ -3291,24 +3332,24 @@ AstNode *AstNode::eval_const_function(AstNode *fcall)
continue; continue;
if (stmt->children.at(1)->type != AST_CONSTANT) if (stmt->children.at(1)->type != AST_CONSTANT)
log_error("Non-constant expression in constant function at %s:%d (called from %s:%d). X\n", log_file_error(stmt->filename, stmt->linenum, "Non-constant expression in constant function\n%s:%d: ... called from here. X\n",
stmt->filename.c_str(), stmt->linenum, fcall->filename.c_str(), fcall->linenum); fcall->filename.c_str(), fcall->linenum);
if (stmt->children.at(0)->type != AST_IDENTIFIER) if (stmt->children.at(0)->type != AST_IDENTIFIER)
log_error("Unsupported composite left hand side in constant function at %s:%d (called from %s:%d).\n", log_file_error(stmt->filename, stmt->linenum, "Unsupported composite left hand side in constant function\n%s:%d: ... called from here.\n",
stmt->filename.c_str(), stmt->linenum, fcall->filename.c_str(), fcall->linenum); fcall->filename.c_str(), fcall->linenum);
if (!variables.count(stmt->children.at(0)->str)) if (!variables.count(stmt->children.at(0)->str))
log_error("Assignment to non-local variable in constant function at %s:%d (called from %s:%d).\n", log_file_error(stmt->filename, stmt->linenum, "Assignment to non-local variable in constant function\n%s:%d: ... called from here.\n",
stmt->filename.c_str(), stmt->linenum, fcall->filename.c_str(), fcall->linenum); fcall->filename.c_str(), fcall->linenum);
if (stmt->children.at(0)->children.empty()) { if (stmt->children.at(0)->children.empty()) {
variables[stmt->children.at(0)->str].val = stmt->children.at(1)->bitsAsConst(variables[stmt->children.at(0)->str].val.bits.size()); variables[stmt->children.at(0)->str].val = stmt->children.at(1)->bitsAsConst(variables[stmt->children.at(0)->str].val.bits.size());
} else { } else {
AstNode *range = stmt->children.at(0)->children.at(0); AstNode *range = stmt->children.at(0)->children.at(0);
if (!range->range_valid) if (!range->range_valid)
log_error("Non-constant range in %s:%d (called from %s:%d).\n", log_file_error(range->filename, range->linenum, "Non-constant range\n%s:%d: ... called from here.\n",
range->filename.c_str(), range->linenum, fcall->filename.c_str(), fcall->linenum); fcall->filename.c_str(), fcall->linenum);
int offset = min(range->range_left, range->range_right); int offset = min(range->range_left, range->range_right);
int width = std::abs(range->range_left - range->range_right) + 1; int width = std::abs(range->range_left - range->range_right) + 1;
varinfo_t &v = variables[stmt->children.at(0)->str]; varinfo_t &v = variables[stmt->children.at(0)->str];
@ -3339,8 +3380,8 @@ AstNode *AstNode::eval_const_function(AstNode *fcall)
while (cond->simplify(true, false, false, 1, -1, false, true)) { } while (cond->simplify(true, false, false, 1, -1, false, true)) { }
if (cond->type != AST_CONSTANT) if (cond->type != AST_CONSTANT)
log_error("Non-constant expression in constant function at %s:%d (called from %s:%d).\n", log_file_error(stmt->filename, stmt->linenum, "Non-constant expression in constant function\n%s:%d: ... called from here.\n",
stmt->filename.c_str(), stmt->linenum, fcall->filename.c_str(), fcall->linenum); fcall->filename.c_str(), fcall->linenum);
if (cond->asBool()) { if (cond->asBool()) {
block->children.insert(block->children.begin(), stmt->children.at(1)->clone()); block->children.insert(block->children.begin(), stmt->children.at(1)->clone());
@ -3360,8 +3401,8 @@ AstNode *AstNode::eval_const_function(AstNode *fcall)
while (num->simplify(true, false, false, 1, -1, false, true)) { } while (num->simplify(true, false, false, 1, -1, false, true)) { }
if (num->type != AST_CONSTANT) if (num->type != AST_CONSTANT)
log_error("Non-constant expression in constant function at %s:%d (called from %s:%d).\n", log_file_error(stmt->filename, stmt->linenum, "Non-constant expression in constant function\n%s:%d: ... called from here.\n",
stmt->filename.c_str(), stmt->linenum, fcall->filename.c_str(), fcall->linenum); fcall->filename.c_str(), fcall->linenum);
block->children.erase(block->children.begin()); block->children.erase(block->children.begin());
for (int i = 0; i < num->bitsAsConst().as_int(); i++) for (int i = 0; i < num->bitsAsConst().as_int(); i++)
@ -3398,8 +3439,8 @@ AstNode *AstNode::eval_const_function(AstNode *fcall)
while (cond->simplify(true, false, false, 1, -1, false, true)) { } while (cond->simplify(true, false, false, 1, -1, false, true)) { }
if (cond->type != AST_CONSTANT) if (cond->type != AST_CONSTANT)
log_error("Non-constant expression in constant function at %s:%d (called from %s:%d).\n", log_file_error(stmt->filename, stmt->linenum, "Non-constant expression in constant function\n%s:%d: ... called from here.\n",
stmt->filename.c_str(), stmt->linenum, fcall->filename.c_str(), fcall->linenum); fcall->filename.c_str(), fcall->linenum);
found_match = cond->asBool(); found_match = cond->asBool();
delete cond; delete cond;
@ -3428,8 +3469,8 @@ AstNode *AstNode::eval_const_function(AstNode *fcall)
continue; continue;
} }
log_error("Unsupported language construct in constant function at %s:%d (called from %s:%d).\n", log_file_error(stmt->filename, stmt->linenum, "Unsupported language construct in constant function\n%s:%d: ... called from here.\n",
stmt->filename.c_str(), stmt->linenum, fcall->filename.c_str(), fcall->linenum); fcall->filename.c_str(), fcall->linenum);
log_abort(); log_abort();
} }
@ -3446,4 +3487,3 @@ AstNode *AstNode::eval_const_function(AstNode *fcall)
} }
YOSYS_NAMESPACE_END YOSYS_NAMESPACE_END

44
frontends/blif/blifparse.cc
View File

@ -83,7 +83,9 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo
RTLIL::Module *module = nullptr; RTLIL::Module *module = nullptr;
RTLIL::Const *lutptr = NULL; RTLIL::Const *lutptr = NULL;
RTLIL::Cell *sopcell = NULL; RTLIL::Cell *sopcell = NULL;
RTLIL::Cell *lastcell = nullptr;
RTLIL::State lut_default_state = RTLIL::State::Sx; RTLIL::State lut_default_state = RTLIL::State::Sx;
std::string err_reason;
int blif_maxnum = 0, sopmode = -1; int blif_maxnum = 0, sopmode = -1;
auto blif_wire = [&](const std::string &wire_name) -> Wire* auto blif_wire = [&](const std::string &wire_name) -> Wire*
@ -159,6 +161,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo
if (module != nullptr) if (module != nullptr)
goto error; goto error;
module = new RTLIL::Module; module = new RTLIL::Module;
lastcell = nullptr;
module->name = RTLIL::escape_id(strtok(NULL, " \t\r\n")); module->name = RTLIL::escape_id(strtok(NULL, " \t\r\n"));
obj_attributes = &module->attributes; obj_attributes = &module->attributes;
obj_parameters = nullptr; obj_parameters = nullptr;
@ -232,6 +235,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo
} }
module = nullptr; module = nullptr;
lastcell = nullptr;
obj_attributes = nullptr; obj_attributes = nullptr;
obj_parameters = nullptr; obj_parameters = nullptr;
continue; continue;
@ -264,6 +268,22 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo
continue; continue;
} }
if (!strcmp(cmd, ".cname"))
{
char *p = strtok(NULL, " \t\r\n");
if (p == NULL)
goto error;
if(lastcell == nullptr || module == nullptr)
{
err_reason = stringf("No primative object to attach .cname %s.", p);
goto error_with_reason;
}
module->rename(lastcell, p);
continue;
}
if (!strcmp(cmd, ".attr") || !strcmp(cmd, ".param")) { if (!strcmp(cmd, ".attr") || !strcmp(cmd, ".param")) {
char *n = strtok(NULL, " \t\r\n"); char *n = strtok(NULL, " \t\r\n");
char *v = strtok(NULL, "\r\n"); char *v = strtok(NULL, "\r\n");
@ -281,12 +301,16 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo
const_v.bits[i] = v[n-i-1] != '0' ? State::S1 : State::S0; const_v.bits[i] = v[n-i-1] != '0' ? State::S1 : State::S0;
} }
if (!strcmp(cmd, ".attr")) { if (!strcmp(cmd, ".attr")) {
if (obj_attributes == nullptr) if (obj_attributes == nullptr) {
goto error; err_reason = stringf("No object to attach .attr too.");
goto error_with_reason;
}
(*obj_attributes)[id_n] = const_v; (*obj_attributes)[id_n] = const_v;
} else { } else {
if (obj_parameters == nullptr) if (obj_parameters == nullptr) {
goto error; err_reason = stringf("No object to attach .param too.");
goto error_with_reason;
}
(*obj_parameters)[id_n] = const_v; (*obj_parameters)[id_n] = const_v;
} }
continue; continue;
@ -331,6 +355,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo
} }
} }
lastcell = cell;
obj_attributes = &cell->attributes; obj_attributes = &cell->attributes;
obj_parameters = &cell->parameters; obj_parameters = &cell->parameters;
continue; continue;
@ -383,6 +408,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo
cell->setPort(it.first, sig); cell->setPort(it.first, sig);
} }
lastcell = cell;
obj_attributes = &cell->attributes; obj_attributes = &cell->attributes;
obj_parameters = &cell->parameters; obj_parameters = &cell->parameters;
continue; continue;
@ -391,7 +417,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo
obj_attributes = nullptr; obj_attributes = nullptr;
obj_parameters = nullptr; obj_parameters = nullptr;
if (!strcmp(cmd, ".barbuf")) if (!strcmp(cmd, ".barbuf") || !strcmp(cmd, ".conn"))
{ {
char *p = strtok(NULL, " \t\r\n"); char *p = strtok(NULL, " \t\r\n");
if (p == NULL) if (p == NULL)
@ -459,6 +485,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo
sopcell->setPort("\\A", input_sig); sopcell->setPort("\\A", input_sig);
sopcell->setPort("\\Y", output_sig); sopcell->setPort("\\Y", output_sig);
sopmode = -1; sopmode = -1;
lastcell = sopcell;
} }
else else
{ {
@ -469,6 +496,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo
cell->setPort("\\Y", output_sig); cell->setPort("\\Y", output_sig);
lutptr = &cell->parameters.at("\\LUT"); lutptr = &cell->parameters.at("\\LUT");
lut_default_state = RTLIL::State::Sx; lut_default_state = RTLIL::State::Sx;
lastcell = cell;
} }
continue; continue;
} }
@ -546,11 +574,13 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo
error: error:
log_error("Syntax error in line %d!\n", line_count); log_error("Syntax error in line %d!\n", line_count);
error_with_reason:
log_error("Syntax error in line %d: %s\n", line_count, err_reason.c_str());
} }
struct BlifFrontend : public Frontend { struct BlifFrontend : public Frontend {
BlifFrontend() : Frontend("blif", "read BLIF file") { } BlifFrontend() : Frontend("blif", "read BLIF file") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -566,7 +596,7 @@ struct BlifFrontend : public Frontend {
log(" multi-bit port 'name'.\n"); log(" multi-bit port 'name'.\n");
log("\n"); log("\n");
} }
virtual void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
bool sop_mode = false; bool sop_mode = false;
bool wideports = false; bool wideports = false;

4
frontends/ilang/ilang_frontend.cc
View File

@ -35,7 +35,7 @@ YOSYS_NAMESPACE_BEGIN
struct IlangFrontend : public Frontend { struct IlangFrontend : public Frontend {
IlangFrontend() : Frontend("ilang", "read modules from ilang file") { } IlangFrontend() : Frontend("ilang", "read modules from ilang file") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -45,7 +45,7 @@ struct IlangFrontend : public Frontend {
log("representation of a design in yosys's internal format.)\n"); log("representation of a design in yosys's internal format.)\n");
log("\n"); log("\n");
} }
virtual void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
log_header(design, "Executing ILANG frontend.\n"); log_header(design, "Executing ILANG frontend.\n");
extra_args(f, filename, args, 1); extra_args(f, filename, args, 1);

4
frontends/json/jsonparse.cc
View File

@ -494,7 +494,7 @@ void json_import(Design *design, string &modname, JsonNode *node)
struct JsonFrontend : public Frontend { struct JsonFrontend : public Frontend {
JsonFrontend() : Frontend("json", "read JSON file") { } JsonFrontend() : Frontend("json", "read JSON file") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -504,7 +504,7 @@ struct JsonFrontend : public Frontend {
log("for a description of the file format.\n"); log("for a description of the file format.\n");
log("\n"); log("\n");
} }
virtual void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
log_header(design, "Executing JSON frontend.\n"); log_header(design, "Executing JSON frontend.\n");

4
frontends/liberty/liberty.cc
View File

@ -452,7 +452,7 @@ void parse_type_map(std::map<std::string, std::tuple<int, int, bool>> &type_map,
struct LibertyFrontend : public Frontend { struct LibertyFrontend : public Frontend {
LibertyFrontend() : Frontend("liberty", "read cells from liberty file") { } LibertyFrontend() : Frontend("liberty", "read cells from liberty file") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -485,7 +485,7 @@ struct LibertyFrontend : public Frontend {
log(" set the specified attribute (to the value 1) on all loaded modules\n"); log(" set the specified attribute (to the value 1) on all loaded modules\n");
log("\n"); log("\n");
} }
virtual void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
bool flag_lib = false; bool flag_lib = false;
bool flag_nooverwrite = false; bool flag_nooverwrite = false;

137
frontends/verific/verific.cc
View File

@ -65,6 +65,8 @@ int verific_verbose;
bool verific_import_pending; bool verific_import_pending;
string verific_error_msg; string verific_error_msg;
vector<string> verific_incdirs, verific_libdirs;
void msg_func(msg_type_t msg_type, const char *message_id, linefile_type linefile, const char *msg, va_list args) void msg_func(msg_type_t msg_type, const char *message_id, linefile_type linefile, const char *msg, va_list args)
{ {
string message_prefix = stringf("VERIFIC-%s [%s] ", string message_prefix = stringf("VERIFIC-%s [%s] ",
@ -1658,6 +1660,8 @@ void verific_import(Design *design, std::string top)
veri_file::Reset(); veri_file::Reset();
vhdl_file::Reset(); vhdl_file::Reset();
Libset::Reset(); Libset::Reset();
verific_incdirs.clear();
verific_libdirs.clear();
verific_import_pending = false; verific_import_pending = false;
if (!verific_error_msg.empty()) if (!verific_error_msg.empty())
@ -1681,7 +1685,7 @@ bool check_noverific_env()
struct VerificPass : public Pass { struct VerificPass : public Pass {
VerificPass() : Pass("verific", "load Verilog and VHDL designs using Verific") { } VerificPass() : Pass("verific", "load Verilog and VHDL designs using Verific") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -1702,11 +1706,18 @@ struct VerificPass : public Pass {
log("\n"); log("\n");
log("Like -sv, but define FORMAL instead of SYNTHESIS.\n"); log("Like -sv, but define FORMAL instead of SYNTHESIS.\n");
log("\n"); log("\n");
log("\n");
log(" verific {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} <vhdl-file>..\n"); log(" verific {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} <vhdl-file>..\n");
log("\n"); log("\n");
log("Load the specified VHDL files into Verific.\n"); log("Load the specified VHDL files into Verific.\n");
log("\n"); log("\n");
log("\n"); log("\n");
log(" verific -work <libname> {-sv|-vhdl|...} <hdl-file>\n");
log("\n");
log("Load the specified Verilog/SystemVerilog/VHDL file into the specified library.\n");
log("(default library when -work is not present: \"work\")\n");
log("\n");
log("\n");
log(" verific -vlog-incdir <directory>..\n"); log(" verific -vlog-incdir <directory>..\n");
log("\n"); log("\n");
log("Add Verilog include directories.\n"); log("Add Verilog include directories.\n");
@ -1728,6 +1739,15 @@ struct VerificPass : public Pass {
log("Remove Verilog defines previously set with -vlog-define.\n"); log("Remove Verilog defines previously set with -vlog-define.\n");
log("\n"); log("\n");
log("\n"); log("\n");
log(" verific -set-error <msg_id>..\n");
log(" verific -set-warning <msg_id>..\n");
log(" verific -set-info <msg_id>..\n");
log(" verific -set-ignore <msg_id>..\n");
log("\n");
log("Set message severity. <msg_id> is the string in square brackets when a message\n");
log("is printed, such as VERI-1209.\n");
log("\n");
log("\n");
log(" verific -import [options] <top-module>..\n"); log(" verific -import [options] <top-module>..\n");
log("\n"); log("\n");
log("Elaborate the design for the specified top modules, import to Yosys and\n"); log("Elaborate the design for the specified top modules, import to Yosys and\n");
@ -1780,21 +1800,34 @@ struct VerificPass : public Pass {
log("\n"); log("\n");
} }
#ifdef YOSYS_ENABLE_VERIFIC #ifdef YOSYS_ENABLE_VERIFIC
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
static bool set_verific_global_flags = true;
if (check_noverific_env()) if (check_noverific_env())
log_cmd_error("This version of Yosys is built without Verific support.\n"); log_cmd_error("This version of Yosys is built without Verific support.\n");
log_header(design, "Executing VERIFIC (loading SystemVerilog and VHDL designs using Verific).\n"); log_header(design, "Executing VERIFIC (loading SystemVerilog and VHDL designs using Verific).\n");
Message::SetConsoleOutput(0); if (set_verific_global_flags)
Message::RegisterCallBackMsg(msg_func); {
RuntimeFlags::SetVar("db_preserve_user_nets", 1); Message::SetConsoleOutput(0);
RuntimeFlags::SetVar("db_allow_external_nets", 1); Message::RegisterCallBackMsg(msg_func);
RuntimeFlags::SetVar("vhdl_ignore_assertion_statements", 0); RuntimeFlags::SetVar("db_preserve_user_nets", 1);
RuntimeFlags::SetVar("veri_extract_dualport_rams", 0); RuntimeFlags::SetVar("db_allow_external_nets", 1);
RuntimeFlags::SetVar("veri_extract_multiport_rams", 1); RuntimeFlags::SetVar("vhdl_ignore_assertion_statements", 0);
RuntimeFlags::SetVar("db_infer_wide_operators", 1); RuntimeFlags::SetVar("veri_extract_dualport_rams", 0);
RuntimeFlags::SetVar("veri_extract_multiport_rams", 1);
RuntimeFlags::SetVar("db_infer_wide_operators", 1);
// Workaround for VIPER #13851
RuntimeFlags::SetVar("veri_create_name_for_unnamed_gen_block", 1);
// WARNING: instantiating unknown module 'XYZ' (VERI-1063)
Message::SetMessageType("VERI-1063", VERIFIC_ERROR);
set_verific_global_flags = false;
}
verific_verbose = 0; verific_verbose = 0;
@ -1811,16 +1844,39 @@ struct VerificPass : public Pass {
log("Built with Verific %s, released at %s.\n", release_str, release_tmstr); log("Built with Verific %s, released at %s.\n", release_str, release_tmstr);
int argidx = 1; int argidx = 1;
std::string work = "work";
if (GetSize(args) > argidx && (args[argidx] == "-set-error" || args[argidx] == "-set-warning" ||
args[argidx] == "-set-info" || args[argidx] == "-set-ignore"))
{
msg_type_t new_type;
if (args[argidx] == "-set-error")
new_type = VERIFIC_ERROR;
else if (args[argidx] == "-set-warning")
new_type = VERIFIC_WARNING;
else if (args[argidx] == "-set-info")
new_type = VERIFIC_INFO;
else if (args[argidx] == "-set-ignore")
new_type = VERIFIC_IGNORE;
else
log_abort();
for (argidx++; argidx < GetSize(args); argidx++)
Message::SetMessageType(args[argidx].c_str(), new_type);
goto check_error;
}
if (GetSize(args) > argidx && args[argidx] == "-vlog-incdir") { if (GetSize(args) > argidx && args[argidx] == "-vlog-incdir") {
for (argidx++; argidx < GetSize(args); argidx++) for (argidx++; argidx < GetSize(args); argidx++)
veri_file::AddIncludeDir(args[argidx].c_str()); verific_incdirs.push_back(args[argidx]);
goto check_error; goto check_error;
} }
if (GetSize(args) > argidx && args[argidx] == "-vlog-libdir") { if (GetSize(args) > argidx && args[argidx] == "-vlog-libdir") {
for (argidx++; argidx < GetSize(args); argidx++) for (argidx++; argidx < GetSize(args); argidx++)
veri_file::AddYDir(args[argidx].c_str()); verific_libdirs.push_back(args[argidx]);
goto check_error; goto check_error;
} }
@ -1847,6 +1903,15 @@ struct VerificPass : public Pass {
goto check_error; goto check_error;
} }
for (; argidx < GetSize(args); argidx++)
{
if (args[argidx] == "-work" && argidx+1 < GetSize(args)) {
work = args[++argidx];
continue;
}
break;
}
if (GetSize(args) > argidx && (args[argidx] == "-vlog95" || args[argidx] == "-vlog2k" || args[argidx] == "-sv2005" || if (GetSize(args) > argidx && (args[argidx] == "-vlog95" || args[argidx] == "-vlog2k" || args[argidx] == "-sv2005" ||
args[argidx] == "-sv2009" || args[argidx] == "-sv2012" || args[argidx] == "-sv" || args[argidx] == "-formal")) args[argidx] == "-sv2009" || args[argidx] == "-sv2012" || args[argidx] == "-sv" || args[argidx] == "-formal"))
{ {
@ -1886,10 +1951,15 @@ struct VerificPass : public Pass {
} }
} }
for (auto &dir : verific_incdirs)
veri_file::AddIncludeDir(dir.c_str());
for (auto &dir : verific_libdirs)
veri_file::AddYDir(dir.c_str());
while (argidx < GetSize(args)) while (argidx < GetSize(args))
file_names.Insert(args[argidx++].c_str()); file_names.Insert(args[argidx++].c_str());
if (!veri_file::AnalyzeMultipleFiles(&file_names, verilog_mode, "work", veri_file::MFCU)) if (!veri_file::AnalyzeMultipleFiles(&file_names, verilog_mode, work.c_str(), veri_file::MFCU))
log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n"); log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n");
verific_import_pending = true; verific_import_pending = true;
@ -1899,7 +1969,7 @@ struct VerificPass : public Pass {
if (GetSize(args) > argidx && args[argidx] == "-vhdl87") { if (GetSize(args) > argidx && args[argidx] == "-vhdl87") {
vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1987").c_str()); vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1987").c_str());
for (argidx++; argidx < GetSize(args); argidx++) for (argidx++; argidx < GetSize(args); argidx++)
if (!vhdl_file::Analyze(args[argidx].c_str(), "work", vhdl_file::VHDL_87)) if (!vhdl_file::Analyze(args[argidx].c_str(), work.c_str(), vhdl_file::VHDL_87))
log_cmd_error("Reading `%s' in VHDL_87 mode failed.\n", args[argidx].c_str()); log_cmd_error("Reading `%s' in VHDL_87 mode failed.\n", args[argidx].c_str());
verific_import_pending = true; verific_import_pending = true;
goto check_error; goto check_error;
@ -1908,7 +1978,7 @@ struct VerificPass : public Pass {
if (GetSize(args) > argidx && args[argidx] == "-vhdl93") { if (GetSize(args) > argidx && args[argidx] == "-vhdl93") {
vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1993").c_str()); vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1993").c_str());
for (argidx++; argidx < GetSize(args); argidx++) for (argidx++; argidx < GetSize(args); argidx++)
if (!vhdl_file::Analyze(args[argidx].c_str(), "work", vhdl_file::VHDL_93)) if (!vhdl_file::Analyze(args[argidx].c_str(), work.c_str(), vhdl_file::VHDL_93))
log_cmd_error("Reading `%s' in VHDL_93 mode failed.\n", args[argidx].c_str()); log_cmd_error("Reading `%s' in VHDL_93 mode failed.\n", args[argidx].c_str());
verific_import_pending = true; verific_import_pending = true;
goto check_error; goto check_error;
@ -1917,7 +1987,7 @@ struct VerificPass : public Pass {
if (GetSize(args) > argidx && args[argidx] == "-vhdl2k") { if (GetSize(args) > argidx && args[argidx] == "-vhdl2k") {
vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1993").c_str()); vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1993").c_str());
for (argidx++; argidx < GetSize(args); argidx++) for (argidx++; argidx < GetSize(args); argidx++)
if (!vhdl_file::Analyze(args[argidx].c_str(), "work", vhdl_file::VHDL_2K)) if (!vhdl_file::Analyze(args[argidx].c_str(), work.c_str(), vhdl_file::VHDL_2K))
log_cmd_error("Reading `%s' in VHDL_2K mode failed.\n", args[argidx].c_str()); log_cmd_error("Reading `%s' in VHDL_2K mode failed.\n", args[argidx].c_str());
verific_import_pending = true; verific_import_pending = true;
goto check_error; goto check_error;
@ -1926,7 +1996,7 @@ struct VerificPass : public Pass {
if (GetSize(args) > argidx && (args[argidx] == "-vhdl2008" || args[argidx] == "-vhdl")) { if (GetSize(args) > argidx && (args[argidx] == "-vhdl2008" || args[argidx] == "-vhdl")) {
vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_2008").c_str()); vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_2008").c_str());
for (argidx++; argidx < GetSize(args); argidx++) for (argidx++; argidx < GetSize(args); argidx++)
if (!vhdl_file::Analyze(args[argidx].c_str(), "work", vhdl_file::VHDL_2008)) if (!vhdl_file::Analyze(args[argidx].c_str(), work.c_str(), vhdl_file::VHDL_2008))
log_cmd_error("Reading `%s' in VHDL_2008 mode failed.\n", args[argidx].c_str()); log_cmd_error("Reading `%s' in VHDL_2008 mode failed.\n", args[argidx].c_str());
verific_import_pending = true; verific_import_pending = true;
goto check_error; goto check_error;
@ -2036,8 +2106,8 @@ struct VerificPass : public Pass {
#else #else
log("Running hier_tree::ElaborateAll().\n"); log("Running hier_tree::ElaborateAll().\n");
VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary("work", 1); VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work.c_str(), 1);
VeriLibrary *veri_lib = veri_file::GetLibrary("work", 1); VeriLibrary *veri_lib = veri_file::GetLibrary(work.c_str(), 1);
Array veri_libs, vhdl_libs; Array veri_libs, vhdl_libs;
if (vhdl_lib) vhdl_libs.InsertLast(vhdl_lib); if (vhdl_lib) vhdl_libs.InsertLast(vhdl_lib);
@ -2084,7 +2154,7 @@ struct VerificPass : public Pass {
continue; continue;
} }
VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary("work", 1); VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work.c_str(), 1);
VhdlDesignUnit *vhdl_unit = vhdl_lib->GetPrimUnit(name); VhdlDesignUnit *vhdl_unit = vhdl_lib->GetPrimUnit(name);
if (vhdl_unit) { if (vhdl_unit) {
log("Adding VHDL unit '%s' to elaboration queue.\n", name); log("Adding VHDL unit '%s' to elaboration queue.\n", name);
@ -2139,6 +2209,8 @@ struct VerificPass : public Pass {
veri_file::Reset(); veri_file::Reset();
vhdl_file::Reset(); vhdl_file::Reset();
Libset::Reset(); Libset::Reset();
verific_incdirs.clear();
verific_libdirs.clear();
verific_import_pending = false; verific_import_pending = false;
goto check_error; goto check_error;
} }
@ -2151,7 +2223,7 @@ struct VerificPass : public Pass {
} }
#else /* YOSYS_ENABLE_VERIFIC */ #else /* YOSYS_ENABLE_VERIFIC */
virtual void execute(std::vector<std::string>, RTLIL::Design *) { void execute(std::vector<std::string>, RTLIL::Design *) YS_OVERRIDE {
log_cmd_error("This version of Yosys is built without Verific support.\n"); log_cmd_error("This version of Yosys is built without Verific support.\n");
} }
#endif #endif
@ -2159,7 +2231,7 @@ struct VerificPass : public Pass {
struct ReadPass : public Pass { struct ReadPass : public Pass {
ReadPass() : Pass("read", "load HDL designs") { } ReadPass() : Pass("read", "load HDL designs") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -2186,8 +2258,13 @@ struct ReadPass : public Pass {
log("\n"); log("\n");
log("Unset global Verilog/SystemVerilog defines.\n"); log("Unset global Verilog/SystemVerilog defines.\n");
log("\n"); log("\n");
log("\n");
log(" read -incdir <directory>\n");
log("\n");
log("Add directory to global Verilog/SystemVerilog include directories.\n");
log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
if (args.size() < 2) if (args.size() < 2)
log_cmd_error("Missing mode parameter.\n"); log_cmd_error("Missing mode parameter.\n");
@ -2263,6 +2340,20 @@ struct ReadPass : public Pass {
return; return;
} }
if (args[1] == "-incdir") {
if (use_verific) {
args[0] = "verific";
args[1] = "-vlog-incdir";
Pass::call(design, args);
}
args[0] = "verilog_defaults";
args[1] = "-add";
for (int i = 2; i < GetSize(args); i++)
args[i] = "-I" + args[i];
Pass::call(design, args);
return;
}
log_cmd_error("Missing or unsupported mode parameter.\n"); log_cmd_error("Missing or unsupported mode parameter.\n");
} }
} ReadPass; } ReadPass;

6
frontends/verific/verificsva.cc
View File

@ -1517,9 +1517,11 @@ struct VerificSvaImporter
Instance *consequent_inst = net_to_ast_driver(consequent_net); Instance *consequent_inst = net_to_ast_driver(consequent_net);
if (consequent_inst->Type() != PRIM_SVA_S_EVENTUALLY && consequent_inst->Type() != PRIM_SVA_EVENTUALLY) { if (consequent_inst == nullptr)
return false;
if (consequent_inst->Type() != PRIM_SVA_S_EVENTUALLY && consequent_inst->Type() != PRIM_SVA_EVENTUALLY)
return false; return false;
}
if (mode_cover || mode_trigger) if (mode_cover || mode_trigger)
parser_error(consequent_inst); parser_error(consequent_inst);

8
frontends/verilog/const2ast.cc
View File

@ -49,8 +49,7 @@ static int my_decimal_div_by_two(std::vector<uint8_t> &digits)
int carry = 0; int carry = 0;
for (size_t i = 0; i < digits.size(); i++) { for (size_t i = 0; i < digits.size(); i++) {
if (digits[i] >= 10) if (digits[i] >= 10)
log_error("Invalid use of [a-fxz?] in decimal constant at %s:%d.\n", log_file_error(current_filename, get_line_num(), "Invalid use of [a-fxz?] in decimal constant.\n");
current_filename.c_str(), get_line_num());
digits[i] += carry * 10; digits[i] += carry * 10;
carry = digits[i] % 2; carry = digits[i] % 2;
digits[i] /= 2; digits[i] /= 2;
@ -105,8 +104,8 @@ static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int le
int bits_per_digit = my_ilog2(base-1); int bits_per_digit = my_ilog2(base-1);
for (auto it = digits.rbegin(), e = digits.rend(); it != e; it++) { for (auto it = digits.rbegin(), e = digits.rend(); it != e; it++) {
if (*it > (base-1) && *it < 0xf0) if (*it > (base-1) && *it < 0xf0)
log_error("Digit larger than %d used in in base-%d constant at %s:%d.\n", log_file_error(current_filename, get_line_num(), "Digit larger than %d used in in base-%d constant.\n",
base-1, base, current_filename.c_str(), get_line_num()); base-1, base);
for (int i = 0; i < bits_per_digit; i++) { for (int i = 0; i < bits_per_digit; i++) {
int bitmask = 1 << i; int bitmask = 1 << i;
if (*it == 0xf0) if (*it == 0xf0)
@ -238,4 +237,3 @@ AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type, bool warn
} }
YOSYS_NAMESPACE_END YOSYS_NAMESPACE_END

20
frontends/verilog/verilog_frontend.cc
View File

@ -42,14 +42,14 @@ static std::list<std::vector<std::string>> verilog_defaults_stack;
static void error_on_dpi_function(AST::AstNode *node) static void error_on_dpi_function(AST::AstNode *node)
{ {
if (node->type == AST::AST_DPI_FUNCTION) if (node->type == AST::AST_DPI_FUNCTION)
log_error("Found DPI function %s at %s:%d.\n", node->str.c_str(), node->filename.c_str(), node->linenum); log_file_error(node->filename, node->linenum, "Found DPI function %s.\n", node->str.c_str());
for (auto child : node->children) for (auto child : node->children)
error_on_dpi_function(child); error_on_dpi_function(child);
} }
struct VerilogFrontend : public Frontend { struct VerilogFrontend : public Frontend {
VerilogFrontend() : Frontend("verilog", "read modules from Verilog file") { } VerilogFrontend() : Frontend("verilog", "read modules from Verilog file") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -180,7 +180,7 @@ struct VerilogFrontend : public Frontend {
log("supported by the Yosys Verilog front-end.\n"); log("supported by the Yosys Verilog front-end.\n");
log("\n"); log("\n");
} }
virtual void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
bool flag_dump_ast1 = false; bool flag_dump_ast1 = false;
bool flag_dump_ast2 = false; bool flag_dump_ast2 = false;
@ -395,7 +395,7 @@ struct VerilogFrontend : public Frontend {
struct VerilogDefaults : public Pass { struct VerilogDefaults : public Pass {
VerilogDefaults() : Pass("verilog_defaults", "set default options for read_verilog") { } VerilogDefaults() : Pass("verilog_defaults", "set default options for read_verilog") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -416,7 +416,7 @@ struct VerilogDefaults : public Pass {
log("not imply -clear.\n"); log("not imply -clear.\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design*) void execute(std::vector<std::string> args, RTLIL::Design*) YS_OVERRIDE
{ {
if (args.size() < 2) if (args.size() < 2)
cmd_error(args, 1, "Missing argument."); cmd_error(args, 1, "Missing argument.");
@ -453,7 +453,7 @@ struct VerilogDefaults : public Pass {
struct VerilogDefines : public Pass { struct VerilogDefines : public Pass {
VerilogDefines() : Pass("verilog_defines", "define and undefine verilog defines") { } VerilogDefines() : Pass("verilog_defines", "define and undefine verilog defines") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -469,7 +469,7 @@ struct VerilogDefines : public Pass {
log(" undefine the preprocessor symbol 'name'\n"); log(" undefine the preprocessor symbol 'name'\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
size_t argidx; size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) { for (argidx = 1; argidx < args.size(); argidx++) {
@ -519,13 +519,11 @@ void frontend_verilog_yyerror(char const *fmt, ...)
va_list ap; va_list ap;
char buffer[1024]; char buffer[1024];
char *p = buffer; char *p = buffer;
p += snprintf(p, buffer + sizeof(buffer) - p, "Parser error in line %s:%d: ",
YOSYS_NAMESPACE_PREFIX AST::current_filename.c_str(), frontend_verilog_yyget_lineno());
va_start(ap, fmt); va_start(ap, fmt);
p += vsnprintf(p, buffer + sizeof(buffer) - p, fmt, ap); p += vsnprintf(p, buffer + sizeof(buffer) - p, fmt, ap);
va_end(ap); va_end(ap);
p += snprintf(p, buffer + sizeof(buffer) - p, "\n"); p += snprintf(p, buffer + sizeof(buffer) - p, "\n");
YOSYS_NAMESPACE_PREFIX log_error("%s", buffer); YOSYS_NAMESPACE_PREFIX log_file_error(YOSYS_NAMESPACE_PREFIX AST::current_filename, frontend_verilog_yyget_lineno(),
"%s", buffer);
exit(1); exit(1);
} }

2
frontends/verilog/verilog_lexer.l
View File

@ -192,7 +192,7 @@ YOSYS_NAMESPACE_END
"const" { if (formal_mode) return TOK_CONST; SV_KEYWORD(TOK_CONST); } "const" { if (formal_mode) return TOK_CONST; SV_KEYWORD(TOK_CONST); }
"checker" { if (formal_mode) return TOK_CHECKER; SV_KEYWORD(TOK_CHECKER); } "checker" { if (formal_mode) return TOK_CHECKER; SV_KEYWORD(TOK_CHECKER); }
"endchecker" { if (formal_mode) return TOK_ENDCHECKER; SV_KEYWORD(TOK_ENDCHECKER); } "endchecker" { if (formal_mode) return TOK_ENDCHECKER; SV_KEYWORD(TOK_ENDCHECKER); }
"logic" { SV_KEYWORD(TOK_REG); } "logic" { SV_KEYWORD(TOK_LOGIC); }
"bit" { SV_KEYWORD(TOK_REG); } "bit" { SV_KEYWORD(TOK_REG); }
"eventually" { if (formal_mode) return TOK_EVENTUALLY; SV_KEYWORD(TOK_EVENTUALLY); } "eventually" { if (formal_mode) return TOK_EVENTUALLY; SV_KEYWORD(TOK_EVENTUALLY); }

16
frontends/verilog/verilog_parser.y
View File

@ -105,7 +105,7 @@ static void free_attr(std::map<std::string, AstNode*> *al)
%token ATTR_BEGIN ATTR_END DEFATTR_BEGIN DEFATTR_END %token ATTR_BEGIN ATTR_END DEFATTR_BEGIN DEFATTR_END
%token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM %token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM
%token TOK_PACKAGE TOK_ENDPACKAGE TOK_PACKAGESEP %token TOK_PACKAGE TOK_ENDPACKAGE TOK_PACKAGESEP
%token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_REG %token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_REG TOK_LOGIC
%token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_ALWAYS TOK_INITIAL %token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_ALWAYS TOK_INITIAL
%token TOK_BEGIN TOK_END TOK_IF TOK_ELSE TOK_FOR TOK_WHILE TOK_REPEAT %token TOK_BEGIN TOK_END TOK_IF TOK_ELSE TOK_FOR TOK_WHILE TOK_REPEAT
%token TOK_DPI_FUNCTION TOK_POSEDGE TOK_NEGEDGE TOK_OR TOK_AUTOMATIC %token TOK_DPI_FUNCTION TOK_POSEDGE TOK_NEGEDGE TOK_OR TOK_AUTOMATIC
@ -376,9 +376,10 @@ wire_type:
}; };
wire_type_token_list: wire_type_token_list:
wire_type_token | wire_type_token_list wire_type_token; wire_type_token | wire_type_token_list wire_type_token |
wire_type_token_io ;
wire_type_token: wire_type_token_io:
TOK_INPUT { TOK_INPUT {
astbuf3->is_input = true; astbuf3->is_input = true;
} | } |
@ -388,12 +389,17 @@ wire_type_token:
TOK_INOUT { TOK_INOUT {
astbuf3->is_input = true; astbuf3->is_input = true;
astbuf3->is_output = true; astbuf3->is_output = true;
} | };
wire_type_token:
TOK_WIRE { TOK_WIRE {
} | } |
TOK_REG { TOK_REG {
astbuf3->is_reg = true; astbuf3->is_reg = true;
} | } |
TOK_LOGIC {
astbuf3->is_logic = true;
} |
TOK_INTEGER { TOK_INTEGER {
astbuf3->is_reg = true; astbuf3->is_reg = true;
astbuf3->range_left = 31; astbuf3->range_left = 31;
@ -545,6 +551,7 @@ task_func_decl:
AstNode *outreg = new AstNode(AST_WIRE); AstNode *outreg = new AstNode(AST_WIRE);
outreg->str = *$6; outreg->str = *$6;
outreg->is_signed = $4; outreg->is_signed = $4;
outreg->is_reg = true;
if ($5 != NULL) { if ($5 != NULL) {
outreg->children.push_back($5); outreg->children.push_back($5);
outreg->is_signed = $4 || $5->is_signed; outreg->is_signed = $4 || $5->is_signed;
@ -1024,6 +1031,7 @@ wire_name:
node->port_id = current_function_or_task_port_id++; node->port_id = current_function_or_task_port_id++;
} }
ast_stack.back()->children.push_back(node); ast_stack.back()->children.push_back(node);
delete $1; delete $1;
}; };

6
kernel/celledges.h
View File

@ -1,4 +1,4 @@
/* /* -*- c++ -*-
* yosys -- Yosys Open SYnthesis Suite * yosys -- Yosys Open SYnthesis Suite
* *
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
@ -38,7 +38,7 @@ struct FwdCellEdgesDatabase : AbstractCellEdgesDatabase
dict<SigBit, pool<SigBit>> db; dict<SigBit, pool<SigBit>> db;
FwdCellEdgesDatabase(SigMap &sigmap) : sigmap(sigmap) { } FwdCellEdgesDatabase(SigMap &sigmap) : sigmap(sigmap) { }
virtual void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) override { void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) YS_OVERRIDE {
SigBit from_sigbit = sigmap(cell->getPort(from_port)[from_bit]); SigBit from_sigbit = sigmap(cell->getPort(from_port)[from_bit]);
SigBit to_sigbit = sigmap(cell->getPort(to_port)[to_bit]); SigBit to_sigbit = sigmap(cell->getPort(to_port)[to_bit]);
db[from_sigbit].insert(to_sigbit); db[from_sigbit].insert(to_sigbit);
@ -51,7 +51,7 @@ struct RevCellEdgesDatabase : AbstractCellEdgesDatabase
dict<SigBit, pool<SigBit>> db; dict<SigBit, pool<SigBit>> db;
RevCellEdgesDatabase(SigMap &sigmap) : sigmap(sigmap) { } RevCellEdgesDatabase(SigMap &sigmap) : sigmap(sigmap) { }
virtual void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) override { void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) YS_OVERRIDE {
SigBit from_sigbit = sigmap(cell->getPort(from_port)[from_bit]); SigBit from_sigbit = sigmap(cell->getPort(from_port)[from_bit]);
SigBit to_sigbit = sigmap(cell->getPort(to_port)[to_bit]); SigBit to_sigbit = sigmap(cell->getPort(to_port)[to_bit]);
db[to_sigbit].insert(from_sigbit); db[to_sigbit].insert(from_sigbit);

86
kernel/log.cc
View File

@ -203,7 +203,8 @@ void logv_header(RTLIL::Design *design, const char *format, va_list ap)
log_files.pop_back(); log_files.pop_back();
} }
void logv_warning(const char *format, va_list ap) static void logv_warning_with_prefix(const char *prefix,
const char *format, va_list ap)
{ {
std::string message = vstringf(format, ap); std::string message = vstringf(format, ap);
bool suppressed = false; bool suppressed = false;
@ -214,7 +215,7 @@ void logv_warning(const char *format, va_list ap)
if (suppressed) if (suppressed)
{ {
log("Suppressed warning: %s", message.c_str()); log("Suppressed %s%s", prefix, message.c_str());
} }
else else
{ {
@ -224,7 +225,7 @@ void logv_warning(const char *format, va_list ap)
if (log_warnings.count(message)) if (log_warnings.count(message))
{ {
log("Warning: %s", message.c_str()); log("%s%s", prefix, message.c_str());
log_flush(); log_flush();
} }
else else
@ -232,7 +233,7 @@ void logv_warning(const char *format, va_list ap)
if (log_errfile != NULL && !log_quiet_warnings) if (log_errfile != NULL && !log_quiet_warnings)
log_files.push_back(log_errfile); log_files.push_back(log_errfile);
log("Warning: %s", message.c_str()); log("%s%s", prefix, message.c_str());
log_flush(); log_flush();
if (log_errfile != NULL && !log_quiet_warnings) if (log_errfile != NULL && !log_quiet_warnings)
@ -245,49 +246,30 @@ void logv_warning(const char *format, va_list ap)
} }
} }
void logv_warning(const char *format, va_list ap)
{
logv_warning_with_prefix("Warning: ", format, ap);
}
void logv_warning_noprefix(const char *format, va_list ap) void logv_warning_noprefix(const char *format, va_list ap)
{ {
std::string message = vstringf(format, ap); logv_warning_with_prefix("", format, ap);
bool suppressed = false;
for (auto &re : log_nowarn_regexes)
if (std::regex_search(message, re))
suppressed = true;
if (suppressed)
{
log("%s", message.c_str());
}
else
{
for (auto &re : log_werror_regexes)
if (std::regex_search(message, re))
log_error("%s", message.c_str());
if (log_warnings.count(message))
{
log("%s", message.c_str());
log_flush();
}
else
{
if (log_errfile != NULL && !log_quiet_warnings)
log_files.push_back(log_errfile);
log("%s", message.c_str());
log_flush();
if (log_errfile != NULL && !log_quiet_warnings)
log_files.pop_back();
log_warnings.insert(message);
}
log_warnings_count++;
}
} }
void logv_error(const char *format, va_list ap) void log_file_warning(const std::string &filename, int lineno,
const char *format, ...)
{
va_list ap;
va_start(ap, format);
std::string prefix = stringf("%s:%d: Warning: ",
filename.c_str(), lineno);
logv_warning_with_prefix(prefix.c_str(), format, ap);
va_end(ap);
}
YS_ATTRIBUTE(noreturn)
static void logv_error_with_prefix(const char *prefix,
const char *format, va_list ap)
{ {
#ifdef EMSCRIPTEN #ifdef EMSCRIPTEN
auto backup_log_files = log_files; auto backup_log_files = log_files;
@ -302,7 +284,7 @@ void logv_error(const char *format, va_list ap)
f = stderr; f = stderr;
log_last_error = vstringf(format, ap); log_last_error = vstringf(format, ap);
log("ERROR: %s", log_last_error.c_str()); log("%s%s", prefix, log_last_error.c_str());
log_flush(); log_flush();
if (log_error_atexit) if (log_error_atexit)
@ -318,6 +300,21 @@ void logv_error(const char *format, va_list ap)
#endif #endif
} }
void logv_error(const char *format, va_list ap)
{
logv_error_with_prefix("ERROR: ", format, ap);
}
void log_file_error(const string &filename, int lineno,
const char *format, ...)
{
va_list ap;
va_start(ap, format);
std::string prefix = stringf("%s:%d: ERROR: ",
filename.c_str(), lineno);
logv_error_with_prefix(prefix.c_str(), format, ap);
}
void log(const char *format, ...) void log(const char *format, ...)
{ {
va_list ap; va_list ap;
@ -636,4 +633,3 @@ dict<std::string, std::pair<std::string, int>> get_coverage_data()
#endif #endif
YOSYS_NAMESPACE_END YOSYS_NAMESPACE_END

5
kernel/log.h
View File

@ -73,8 +73,13 @@ YS_NORETURN void logv_error(const char *format, va_list ap) YS_ATTRIBUTE(noretur
void log(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2)); void log(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));
void log_header(RTLIL::Design *design, const char *format, ...) YS_ATTRIBUTE(format(printf, 2, 3)); void log_header(RTLIL::Design *design, const char *format, ...) YS_ATTRIBUTE(format(printf, 2, 3));
void log_warning(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2)); void log_warning(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));
// Log with filename to report a problem in a source file.
void log_file_warning(const std::string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4));
void log_warning_noprefix(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2)); void log_warning_noprefix(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));
YS_NORETURN void log_error(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2), noreturn); YS_NORETURN void log_error(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2), noreturn);
void log_file_error(const string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4), noreturn);
YS_NORETURN void log_cmd_error(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2), noreturn); YS_NORETURN void log_cmd_error(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2), noreturn);
void log_spacer(); void log_spacer();

10
kernel/modtools.h
View File

@ -1,4 +1,4 @@
/* /* -*- c++ -*-
* yosys -- Yosys Open SYnthesis Suite * yosys -- Yosys Open SYnthesis Suite
* *
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
@ -158,7 +158,7 @@ struct ModIndex : public RTLIL::Monitor
#endif #endif
} }
virtual void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, RTLIL::SigSpec &sig) YS_OVERRIDE void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, RTLIL::SigSpec &sig) YS_OVERRIDE
{ {
log_assert(module == cell->module); log_assert(module == cell->module);
@ -169,7 +169,7 @@ struct ModIndex : public RTLIL::Monitor
port_add(cell, port, sig); port_add(cell, port, sig);
} }
virtual void notify_connect(RTLIL::Module *mod YS_ATTRIBUTE(unused), const RTLIL::SigSig &sigsig) YS_OVERRIDE void notify_connect(RTLIL::Module *mod YS_ATTRIBUTE(unused), const RTLIL::SigSig &sigsig) YS_OVERRIDE
{ {
log_assert(module == mod); log_assert(module == mod);
@ -214,13 +214,13 @@ struct ModIndex : public RTLIL::Monitor
} }
} }
virtual void notify_connect(RTLIL::Module *mod YS_ATTRIBUTE(unused), const std::vector<RTLIL::SigSig>&) YS_OVERRIDE void notify_connect(RTLIL::Module *mod YS_ATTRIBUTE(unused), const std::vector<RTLIL::SigSig>&) YS_OVERRIDE
{ {
log_assert(module == mod); log_assert(module == mod);
auto_reload_module = true; auto_reload_module = true;
} }
virtual void notify_blackout(RTLIL::Module *mod YS_ATTRIBUTE(unused)) YS_OVERRIDE void notify_blackout(RTLIL::Module *mod YS_ATTRIBUTE(unused)) YS_OVERRIDE
{ {
log_assert(module == mod); log_assert(module == mod);
auto_reload_module = true; auto_reload_module = true;

11
kernel/register.cc
View File

@ -615,7 +615,7 @@ static struct CellHelpMessages {
struct HelpPass : public Pass { struct HelpPass : public Pass {
HelpPass() : Pass("help", "display help messages") { } HelpPass() : Pass("help", "display help messages") { }
virtual void help() void help() YS_OVERRIDE
{ {
log("\n"); log("\n");
log(" help ................ list all commands\n"); log(" help ................ list all commands\n");
@ -684,7 +684,7 @@ struct HelpPass : public Pass {
fclose(f); fclose(f);
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design*) void execute(std::vector<std::string> args, RTLIL::Design*) YS_OVERRIDE
{ {
if (args.size() == 1) { if (args.size() == 1) {
log("\n"); log("\n");
@ -768,7 +768,7 @@ struct HelpPass : public Pass {
struct EchoPass : public Pass { struct EchoPass : public Pass {
EchoPass() : Pass("echo", "turning echoing back of commands on and off") { } EchoPass() : Pass("echo", "turning echoing back of commands on and off") { }
virtual void help() void help() YS_OVERRIDE
{ {
log("\n"); log("\n");
log(" echo on\n"); log(" echo on\n");
@ -781,7 +781,7 @@ struct EchoPass : public Pass {
log("Do not print all commands to log before executing them. (default)\n"); log("Do not print all commands to log before executing them. (default)\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design*) void execute(std::vector<std::string> args, RTLIL::Design*) YS_OVERRIDE
{ {
if (args.size() > 2) if (args.size() > 2)
cmd_error(args, 2, "Unexpected argument."); cmd_error(args, 2, "Unexpected argument.");
@ -806,10 +806,9 @@ struct MinisatSatSolver : public SatSolver {
MinisatSatSolver() : SatSolver("minisat") { MinisatSatSolver() : SatSolver("minisat") {
yosys_satsolver = this; yosys_satsolver = this;
} }
virtual ezSAT *create() YS_OVERRIDE { ezSAT *create() YS_OVERRIDE {
return new ezMiniSAT(); return new ezMiniSAT();
} }
} MinisatSatSolver; } MinisatSatSolver;
YOSYS_NAMESPACE_END YOSYS_NAMESPACE_END

14
kernel/register.h
View File

@ -1,4 +1,4 @@
/* /* -*- c++ -*-
* yosys -- Yosys Open SYnthesis Suite * yosys -- Yosys Open SYnthesis Suite
* *
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
@ -88,9 +88,9 @@ struct Frontend : Pass
std::string frontend_name; std::string frontend_name;
Frontend(std::string name, std::string short_help = "** document me **"); Frontend(std::string name, std::string short_help = "** document me **");
virtual void run_register() YS_OVERRIDE; void run_register() YS_OVERRIDE;
virtual ~Frontend(); ~Frontend() YS_OVERRIDE;
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE YS_FINAL; void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE YS_FINAL;
virtual void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) = 0; virtual void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) = 0;
static std::vector<std::string> next_args; static std::vector<std::string> next_args;
@ -104,9 +104,9 @@ struct Backend : Pass
{ {
std::string backend_name; std::string backend_name;
Backend(std::string name, std::string short_help = "** document me **"); Backend(std::string name, std::string short_help = "** document me **");
virtual void run_register() YS_OVERRIDE; void run_register() YS_OVERRIDE;
virtual ~Backend(); ~Backend() YS_OVERRIDE;
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE YS_FINAL; void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE YS_FINAL;
virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) = 0; virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) = 0;
void extra_args(std::ostream *&f, std::string &filename, std::vector<std::string> args, size_t argidx); void extra_args(std::ostream *&f, std::string &filename, std::vector<std::string> args, size_t argidx);

2
kernel/rtlil.h
View File

@ -1,4 +1,4 @@
/* /* -*- c++ -*-
* yosys -- Yosys Open SYnthesis Suite * yosys -- Yosys Open SYnthesis Suite
* *
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>

2
kernel/satgen.h
View File

@ -1,4 +1,4 @@
/* /* -*- c++ -*-
* yosys -- Yosys Open SYnthesis Suite * yosys -- Yosys Open SYnthesis Suite
* *
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>

18
kernel/yosys.cc
View File

@ -636,7 +636,7 @@ extern Tcl_Interp *yosys_get_tcl_interp()
struct TclPass : public Pass { struct TclPass : public Pass {
TclPass() : Pass("tcl", "execute a TCL script file") { } TclPass() : Pass("tcl", "execute a TCL script file") { }
virtual void help() { void help() YS_OVERRIDE {
log("\n"); log("\n");
log(" tcl <filename>\n"); log(" tcl <filename>\n");
log("\n"); log("\n");
@ -649,7 +649,7 @@ struct TclPass : public Pass {
log("in order to avoid a name collision with the built in commands.\n"); log("in order to avoid a name collision with the built in commands.\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE {
if (args.size() < 2) if (args.size() < 2)
log_cmd_error("Missing script file.\n"); log_cmd_error("Missing script file.\n");
if (args.size() > 2) if (args.size() > 2)
@ -825,6 +825,8 @@ void run_frontend(std::string filename, std::string command, std::string *backen
command = "vhdl"; command = "vhdl";
else if (filename.size() > 4 && filename.substr(filename.size()-5) == ".blif") else if (filename.size() > 4 && filename.substr(filename.size()-5) == ".blif")
command = "blif"; command = "blif";
else if (filename.size() > 5 && filename.substr(filename.size()-6) == ".eblif")
command = "blif";
else if (filename.size() > 4 && filename.substr(filename.size()-5) == ".json") else if (filename.size() > 4 && filename.substr(filename.size()-5) == ".json")
command = "json"; command = "json";
else if (filename.size() > 3 && filename.substr(filename.size()-3) == ".il") else if (filename.size() > 3 && filename.substr(filename.size()-3) == ".il")
@ -1111,7 +1113,7 @@ void shell(RTLIL::Design *design)
struct ShellPass : public Pass { struct ShellPass : public Pass {
ShellPass() : Pass("shell", "enter interactive command mode") { } ShellPass() : Pass("shell", "enter interactive command mode") { }
virtual void help() { void help() YS_OVERRIDE {
log("\n"); log("\n");
log(" shell\n"); log(" shell\n");
log("\n"); log("\n");
@ -1143,7 +1145,7 @@ struct ShellPass : public Pass {
log("Press Ctrl-D or type 'exit' to leave the interactive shell.\n"); log("Press Ctrl-D or type 'exit' to leave the interactive shell.\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE {
extra_args(args, 1, design, false); extra_args(args, 1, design, false);
shell(design); shell(design);
} }
@ -1152,7 +1154,7 @@ struct ShellPass : public Pass {
#if defined(YOSYS_ENABLE_READLINE) || defined(YOSYS_ENABLE_EDITLINE) #if defined(YOSYS_ENABLE_READLINE) || defined(YOSYS_ENABLE_EDITLINE)
struct HistoryPass : public Pass { struct HistoryPass : public Pass {
HistoryPass() : Pass("history", "show last interactive commands") { } HistoryPass() : Pass("history", "show last interactive commands") { }
virtual void help() { void help() YS_OVERRIDE {
log("\n"); log("\n");
log(" history\n"); log(" history\n");
log("\n"); log("\n");
@ -1161,7 +1163,7 @@ struct HistoryPass : public Pass {
log("from executed scripts.\n"); log("from executed scripts.\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE {
extra_args(args, 1, design, false); extra_args(args, 1, design, false);
#ifdef YOSYS_ENABLE_READLINE #ifdef YOSYS_ENABLE_READLINE
for(HIST_ENTRY **list = history_list(); *list != NULL; list++) for(HIST_ENTRY **list = history_list(); *list != NULL; list++)
@ -1176,7 +1178,7 @@ struct HistoryPass : public Pass {
struct ScriptCmdPass : public Pass { struct ScriptCmdPass : public Pass {
ScriptCmdPass() : Pass("script", "execute commands from script file") { } ScriptCmdPass() : Pass("script", "execute commands from script file") { }
virtual void help() { void help() YS_OVERRIDE {
log("\n"); log("\n");
log(" script <filename> [<from_label>:<to_label>]\n"); log(" script <filename> [<from_label>:<to_label>]\n");
log("\n"); log("\n");
@ -1191,7 +1193,7 @@ struct ScriptCmdPass : public Pass {
log("marked with that label (until the next label) is executed.\n"); log("marked with that label (until the next label) is executed.\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE {
if (args.size() < 2) if (args.size() < 2)
log_cmd_error("Missing script file.\n"); log_cmd_error("Missing script file.\n");
else if (args.size() == 2) else if (args.size() == 2)

2
kernel/yosys.h
View File

@ -1,4 +1,4 @@
/* /* -*- c++ -*-
* yosys -- Yosys Open SYnthesis Suite * yosys -- Yosys Open SYnthesis Suite
* *
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>

2
manual/CHAPTER_Prog/stubnets.cc
View File

@ -98,7 +98,7 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re
// each pass contains a singleton object that is derived from Pass // each pass contains a singleton object that is derived from Pass
struct StubnetsPass : public Pass { struct StubnetsPass : public Pass {
StubnetsPass() : Pass("stubnets") { } StubnetsPass() : Pass("stubnets") { }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
// variables to mirror information from passed options // variables to mirror information from passed options
bool report_bits = 0; bool report_bits = 0;

6
manual/PRESENTATION_Prog/my_cmd.cc
View File

@ -6,7 +6,7 @@ PRIVATE_NAMESPACE_BEGIN
struct MyPass : public Pass { struct MyPass : public Pass {
MyPass() : Pass("my_cmd", "just a simple test") { } MyPass() : Pass("my_cmd", "just a simple test") { }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
log("Arguments to my_cmd:\n"); log("Arguments to my_cmd:\n");
for (auto &arg : args) for (auto &arg : args)
@ -22,7 +22,7 @@ struct MyPass : public Pass {
struct Test1Pass : public Pass { struct Test1Pass : public Pass {
Test1Pass() : Pass("test1", "creating the absval module") { } Test1Pass() : Pass("test1", "creating the absval module") { }
virtual void execute(std::vector<std::string>, RTLIL::Design *design) void execute(std::vector<std::string>, RTLIL::Design *design) YS_OVERRIDE
{ {
if (design->has("\\absval") != 0) if (design->has("\\absval") != 0)
log_error("A module with the name absval already exists!\n"); log_error("A module with the name absval already exists!\n");
@ -49,7 +49,7 @@ struct Test1Pass : public Pass {
struct Test2Pass : public Pass { struct Test2Pass : public Pass {
Test2Pass() : Pass("test2", "demonstrating sigmap on test module") { } Test2Pass() : Pass("test2", "demonstrating sigmap on test module") { }
virtual void execute(std::vector<std::string>, RTLIL::Design *design) void execute(std::vector<std::string>, RTLIL::Design *design) YS_OVERRIDE
{ {
if (design->selection_stack.back().empty()) if (design->selection_stack.back().empty())
log_cmd_error("This command can't operator on an empty selection!\n"); log_cmd_error("This command can't operator on an empty selection!\n");

4
passes/cmds/add.cc
View File

@ -83,7 +83,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n
struct AddPass : public Pass { struct AddPass : public Pass {
AddPass() : Pass("add", "add objects to the design") { } AddPass() : Pass("add", "add objects to the design") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -106,7 +106,7 @@ struct AddPass : public Pass {
log("selected modules.\n"); log("selected modules.\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
std::string command; std::string command;
std::string arg_name; std::string arg_name;

4
passes/cmds/blackbox.cc
View File

@ -24,7 +24,7 @@ PRIVATE_NAMESPACE_BEGIN
struct BlackboxPass : public Pass { struct BlackboxPass : public Pass {
BlackboxPass() : Pass("blackbox", "change type of cells in the design") { } BlackboxPass() : Pass("blackbox", "change type of cells in the design") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -34,7 +34,7 @@ struct BlackboxPass : public Pass {
log("module attribute).\n"); log("module attribute).\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
size_t argidx; size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) for (argidx = 1; argidx < args.size(); argidx++)

4
passes/cmds/check.cc
View File

@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN
struct CheckPass : public Pass { struct CheckPass : public Pass {
CheckPass() : Pass("check", "check for obvious problems in the design") { } CheckPass() : Pass("check", "check for obvious problems in the design") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -51,7 +51,7 @@ struct CheckPass : public Pass {
log("problems are found in the current design.\n"); log("problems are found in the current design.\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
int counter = 0; int counter = 0;
bool noinit = false; bool noinit = false;

4
passes/cmds/chformal.cc
View File

@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
struct ChformalPass : public Pass { struct ChformalPass : public Pass {
ChformalPass() : Pass("chformal", "change formal constraints of the design") { } ChformalPass() : Pass("chformal", "change formal constraints of the design") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -62,7 +62,7 @@ struct ChformalPass : public Pass {
log(" change the roles of cells as indicated. this options can be combined\n"); log(" change the roles of cells as indicated. this options can be combined\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
bool assert2assume = false; bool assert2assume = false;
bool assume2assert = false; bool assume2assert = false;

4
passes/cmds/chtype.cc
View File

@ -24,7 +24,7 @@ PRIVATE_NAMESPACE_BEGIN
struct ChtypePass : public Pass { struct ChtypePass : public Pass {
ChtypePass() : Pass("chtype", "change type of cells in the design") { } ChtypePass() : Pass("chtype", "change type of cells in the design") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -40,7 +40,7 @@ struct ChtypePass : public Pass {
log("\n"); log("\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
IdString set_type; IdString set_type;
dict<IdString, IdString> map_types; dict<IdString, IdString> map_types;

4
passes/cmds/connect.cc
View File

@ -43,7 +43,7 @@ static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap &
struct ConnectPass : public Pass { struct ConnectPass : public Pass {
ConnectPass() : Pass("connect", "create or remove connections") { } ConnectPass() : Pass("connect", "create or remove connections") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -75,7 +75,7 @@ struct ConnectPass : public Pass {
log("This command does not operate on module with processes.\n"); log("This command does not operate on module with processes.\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
RTLIL::Module *module = NULL; RTLIL::Module *module = NULL;
for (auto &it : design->modules_) { for (auto &it : design->modules_) {

4
passes/cmds/connwrappers.cc
View File

@ -150,7 +150,7 @@ struct ConnwrappersWorker
struct ConnwrappersPass : public Pass { struct ConnwrappersPass : public Pass {
ConnwrappersPass() : Pass("connwrappers", "match width of input-output port pairs") { } ConnwrappersPass() : Pass("connwrappers", "match width of input-output port pairs") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -172,7 +172,7 @@ struct ConnwrappersPass : public Pass {
log("The options -signed, -unsigned, and -port can be specified multiple times.\n"); log("The options -signed, -unsigned, and -port can be specified multiple times.\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
ConnwrappersWorker worker; ConnwrappersWorker worker;

4
passes/cmds/copy.cc
View File

@ -26,7 +26,7 @@ PRIVATE_NAMESPACE_BEGIN
struct CopyPass : public Pass { struct CopyPass : public Pass {
CopyPass() : Pass("copy", "copy modules in the design") { } CopyPass() : Pass("copy", "copy modules in the design") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -36,7 +36,7 @@ struct CopyPass : public Pass {
log("by this command.\n"); log("by this command.\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
if (args.size() != 3) if (args.size() != 3)
log_cmd_error("Invalid number of arguments!\n"); log_cmd_error("Invalid number of arguments!\n");

4
passes/cmds/cover.cc
View File

@ -35,7 +35,7 @@ PRIVATE_NAMESPACE_BEGIN
struct CoverPass : public Pass { struct CoverPass : public Pass {
CoverPass() : Pass("cover", "print code coverage counters") { } CoverPass() : Pass("cover", "print code coverage counters") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -83,7 +83,7 @@ struct CoverPass : public Pass {
log("Coverage counters are only available in Yosys for Linux.\n"); log("Coverage counters are only available in Yosys for Linux.\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
std::vector<FILE*> out_files; std::vector<FILE*> out_files;
std::vector<std::string> patterns; std::vector<std::string> patterns;

4
passes/cmds/delete.cc
View File

@ -24,7 +24,7 @@ PRIVATE_NAMESPACE_BEGIN
struct DeletePass : public Pass { struct DeletePass : public Pass {
DeletePass() : Pass("delete", "delete objects in the design") { } DeletePass() : Pass("delete", "delete objects in the design") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -40,7 +40,7 @@ struct DeletePass : public Pass {
log("selected wires, thus 'deleting' module ports.\n"); log("selected wires, thus 'deleting' module ports.\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
bool flag_input = false; bool flag_input = false;
bool flag_output = false; bool flag_output = false;

6
passes/cmds/design.cc
View File

@ -27,7 +27,7 @@ std::vector<RTLIL::Design*> pushed_designs;
struct DesignPass : public Pass { struct DesignPass : public Pass {
DesignPass() : Pass("design", "save, restore and reset current design") { } DesignPass() : Pass("design", "save, restore and reset current design") { }
virtual ~DesignPass() { ~DesignPass() YS_OVERRIDE {
for (auto &it : saved_designs) for (auto &it : saved_designs)
delete it.second; delete it.second;
saved_designs.clear(); saved_designs.clear();
@ -35,7 +35,7 @@ struct DesignPass : public Pass {
delete it; delete it;
pushed_designs.clear(); pushed_designs.clear();
} }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -94,7 +94,7 @@ struct DesignPass : public Pass {
log("between calls to 'read_verilog'. This command resets this memory.\n"); log("between calls to 'read_verilog'. This command resets this memory.\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
bool got_mode = false; bool got_mode = false;
bool reset_mode = false; bool reset_mode = false;

4
passes/cmds/edgetypes.cc
View File

@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
struct EdgetypePass : public Pass { struct EdgetypePass : public Pass {
EdgetypePass() : Pass("edgetypes", "list all types of edges in selection") { } EdgetypePass() : Pass("edgetypes", "list all types of edges in selection") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -35,7 +35,7 @@ struct EdgetypePass : public Pass {
log("is a 4-tuple of source and sink cell type and port name.\n"); log("is a 4-tuple of source and sink cell type and port name.\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
size_t argidx; size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) { for (argidx = 1; argidx < args.size(); argidx++) {

4
passes/cmds/logcmd.cc
View File

@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN
struct LogPass : public Pass { struct LogPass : public Pass {
LogPass() : Pass("log", "print text and log files") { } LogPass() : Pass("log", "print text and log files") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -52,7 +52,7 @@ struct LogPass : public Pass {
log(" do not append a newline\n"); log(" do not append a newline\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design*) void execute(std::vector<std::string> args, RTLIL::Design*) YS_OVERRIDE
{ {
size_t argidx; size_t argidx;
bool to_stdout = false; bool to_stdout = false;

4
passes/cmds/ltp.cc
View File

@ -141,7 +141,7 @@ struct LtpWorker
struct LtpPass : public Pass { struct LtpPass : public Pass {
LtpPass() : Pass("ltp", "print longest topological path") { } LtpPass() : Pass("ltp", "print longest topological path") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -154,7 +154,7 @@ struct LtpPass : public Pass {
log(" automatically exclude FF cell types\n"); log(" automatically exclude FF cell types\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
bool noff = false; bool noff = false;

4
passes/cmds/plugin.cc
View File

@ -58,7 +58,7 @@ void load_plugin(std::string, std::vector<std::string>)
struct PluginPass : public Pass { struct PluginPass : public Pass {
PluginPass() : Pass("plugin", "load and list loaded plugins") { } PluginPass() : Pass("plugin", "load and list loaded plugins") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -76,7 +76,7 @@ struct PluginPass : public Pass {
log(" List loaded plugins\n"); log(" List loaded plugins\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
std::string plugin_filename; std::string plugin_filename;
std::vector<std::string> plugin_aliases; std::vector<std::string> plugin_aliases;

4
passes/cmds/qwp.cc
View File

@ -778,7 +778,7 @@ struct QwpWorker
struct QwpPass : public Pass { struct QwpPass : public Pass {
QwpPass() : Pass("qwp", "quadratic wirelength placer") { } QwpPass() : Pass("qwp", "quadratic wirelength placer") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -808,7 +808,7 @@ struct QwpPass : public Pass {
log("dense matrix operations. It is only a toy-placer for small circuits.\n"); log("dense matrix operations. It is only a toy-placer for small circuits.\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
QwpConfig config; QwpConfig config;
xorshift32_state = 123456789; xorshift32_state = 123456789;

4
passes/cmds/rename.cc
View File

@ -54,7 +54,7 @@ static void rename_in_module(RTLIL::Module *module, std::string from_name, std::
struct RenamePass : public Pass { struct RenamePass : public Pass {
RenamePass() : Pass("rename", "rename object in the design") { } RenamePass() : Pass("rename", "rename object in the design") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -81,7 +81,7 @@ struct RenamePass : public Pass {
log("Rename top module.\n"); log("Rename top module.\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
std::string pattern_prefix = "_", pattern_suffix = "_"; std::string pattern_prefix = "_", pattern_suffix = "_";
bool flag_enumerate = false; bool flag_enumerate = false;

4
passes/cmds/scatter.cc
View File

@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN
struct ScatterPass : public Pass { struct ScatterPass : public Pass {
ScatterPass() : Pass("scatter", "add additional intermediate nets") { } ScatterPass() : Pass("scatter", "add additional intermediate nets") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -41,7 +41,7 @@ struct ScatterPass : public Pass {
log("Use the opt_clean command to get rid of the additional nets.\n"); log("Use the opt_clean command to get rid of the additional nets.\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
CellTypes ct(design); CellTypes ct(design);
extra_args(args, 1, design); extra_args(args, 1, design);

4
passes/cmds/scc.cc
View File

@ -218,7 +218,7 @@ struct SccWorker
struct SccPass : public Pass { struct SccPass : public Pass {
SccPass() : Pass("scc", "detect strongly connected components (logic loops)") { } SccPass() : Pass("scc", "detect strongly connected components (logic loops)") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -255,7 +255,7 @@ struct SccPass : public Pass {
log(" that are part of a found logic loop\n"); log(" that are part of a found logic loop\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
std::map<std::string, std::string> setAttr; std::map<std::string, std::string> setAttr;
bool allCellTypes = false; bool allCellTypes = false;

14
passes/cmds/select.cc
View File

@ -950,7 +950,7 @@ PRIVATE_NAMESPACE_BEGIN
struct SelectPass : public Pass { struct SelectPass : public Pass {
SelectPass() : Pass("select", "modify and view the list of selected objects") { } SelectPass() : Pass("select", "modify and view the list of selected objects") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -964,7 +964,7 @@ struct SelectPass : public Pass {
log("list of selected objects.\n"); log("list of selected objects.\n");
log("\n"); log("\n");
log("Note that many commands support an optional [selection] argument that can be\n"); log("Note that many commands support an optional [selection] argument that can be\n");
log("used to override the global selection for the command. The syntax of this\n"); log("used to YS_OVERRIDE the global selection for the command. The syntax of this\n");
log("optional argument is identical to the syntax of the <selection> argument\n"); log("optional argument is identical to the syntax of the <selection> argument\n");
log("described here.\n"); log("described here.\n");
log("\n"); log("\n");
@ -1167,7 +1167,7 @@ struct SelectPass : public Pass {
log(" select */t:SWITCH %%x:+[GATE] */t:SWITCH %%d\n"); log(" select */t:SWITCH %%x:+[GATE] */t:SWITCH %%d\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
bool add_mode = false; bool add_mode = false;
bool del_mode = false; bool del_mode = false;
@ -1470,7 +1470,7 @@ struct SelectPass : public Pass {
struct CdPass : public Pass { struct CdPass : public Pass {
CdPass() : Pass("cd", "a shortcut for 'select -module <name>'") { } CdPass() : Pass("cd", "a shortcut for 'select -module <name>'") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -1496,7 +1496,7 @@ struct CdPass : public Pass {
log("This is just a shortcut for 'select -clear'.\n"); log("This is just a shortcut for 'select -clear'.\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
if (args.size() != 1 && args.size() != 2) if (args.size() != 1 && args.size() != 2)
log_cmd_error("Invalid number of arguments.\n"); log_cmd_error("Invalid number of arguments.\n");
@ -1578,7 +1578,7 @@ static void log_matches(const char *title, Module *module, T list)
struct LsPass : public Pass { struct LsPass : public Pass {
LsPass() : Pass("ls", "list modules or objects in modules") { } LsPass() : Pass("ls", "list modules or objects in modules") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -1589,7 +1589,7 @@ struct LsPass : public Pass {
log("When an active module is selected, this prints a list of objects in the module.\n"); log("When an active module is selected, this prints a list of objects in the module.\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
size_t argidx = 1; size_t argidx = 1;
extra_args(args, argidx, design); extra_args(args, argidx, design);

12
passes/cmds/setattr.cc
View File

@ -56,7 +56,7 @@ static void do_setunset(dict<RTLIL::IdString, RTLIL::Const> &attrs, const std::v
struct SetattrPass : public Pass { struct SetattrPass : public Pass {
SetattrPass() : Pass("setattr", "set/unset attributes on objects") { } SetattrPass() : Pass("setattr", "set/unset attributes on objects") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -69,7 +69,7 @@ struct SetattrPass : public Pass {
log("instead of objects within modules.\n"); log("instead of objects within modules.\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
std::vector<setunset_t> setunset_list; std::vector<setunset_t> setunset_list;
bool flag_mod = false; bool flag_mod = false;
@ -130,7 +130,7 @@ struct SetattrPass : public Pass {
struct SetparamPass : public Pass { struct SetparamPass : public Pass {
SetparamPass() : Pass("setparam", "set/unset parameters on objects") { } SetparamPass() : Pass("setparam", "set/unset parameters on objects") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -142,7 +142,7 @@ struct SetparamPass : public Pass {
log("The -type option can be used to change the cell type of the selected cells.\n"); log("The -type option can be used to change the cell type of the selected cells.\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
vector<setunset_t> setunset_list; vector<setunset_t> setunset_list;
string new_cell_type; string new_cell_type;
@ -188,7 +188,7 @@ struct SetparamPass : public Pass {
struct ChparamPass : public Pass { struct ChparamPass : public Pass {
ChparamPass() : Pass("chparam", "re-evaluate modules with new parameters") { } ChparamPass() : Pass("chparam", "re-evaluate modules with new parameters") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -203,7 +203,7 @@ struct ChparamPass : public Pass {
log("List the available parameters of the selected modules.\n"); log("List the available parameters of the selected modules.\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
std::vector<setunset_t> setunset_list; std::vector<setunset_t> setunset_list;
dict<RTLIL::IdString, RTLIL::Const> new_parameters; dict<RTLIL::IdString, RTLIL::Const> new_parameters;

159
passes/cmds/setundef.cc
View File

@ -33,6 +33,34 @@
USING_YOSYS_NAMESPACE USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN PRIVATE_NAMESPACE_BEGIN
static RTLIL::Wire * add_wire(RTLIL::Module *module, std::string name, int width, bool flag_input, bool flag_output)
{
RTLIL::Wire *wire = NULL;
name = RTLIL::escape_id(name);
if (module->count_id(name) != 0)
{
log("Module %s already has such an object %s.\n", module->name.c_str(), name.c_str());
name += "$";
return add_wire(module, name, width, flag_input, flag_output);
}
else
{
wire = module->addWire(name, width);
wire->port_input = flag_input;
wire->port_output = flag_output;
if (flag_input || flag_output) {
wire->port_id = module->wires_.size();
module->fixup_ports();
}
log("Added wire %s to module %s.\n", name.c_str(), module->name.c_str());
}
return wire;
}
struct SetundefWorker struct SetundefWorker
{ {
int next_bit_mode; int next_bit_mode;
@ -79,7 +107,7 @@ struct SetundefWorker
struct SetundefPass : public Pass { struct SetundefPass : public Pass {
SetundefPass() : Pass("setundef", "replace undef values with defined constants") { } SetundefPass() : Pass("setundef", "replace undef values with defined constants") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -90,6 +118,9 @@ struct SetundefPass : public Pass {
log(" -undriven\n"); log(" -undriven\n");
log(" also set undriven nets to constant values\n"); log(" also set undriven nets to constant values\n");
log("\n"); log("\n");
log(" -expose\n");
log(" also expose undriven nets as inputs (use with -undriven)\n");
log("\n");
log(" -zero\n"); log(" -zero\n");
log(" replace with bits cleared (0)\n"); log(" replace with bits cleared (0)\n");
log("\n"); log("\n");
@ -113,10 +144,11 @@ struct SetundefPass : public Pass {
log(" also create/update init values for flip-flops\n"); log(" also create/update init values for flip-flops\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
bool got_value = false; bool got_value = false;
bool undriven_mode = false; bool undriven_mode = false;
bool expose_mode = false;
bool init_mode = false; bool init_mode = false;
SetundefWorker worker; SetundefWorker worker;
@ -129,6 +161,11 @@ struct SetundefPass : public Pass {
undriven_mode = true; undriven_mode = true;
continue; continue;
} }
if (args[argidx] == "-expose") {
got_value = true;
expose_mode = true;
continue;
}
if (args[argidx] == "-zero") { if (args[argidx] == "-zero") {
got_value = true; got_value = true;
worker.next_bit_mode = MODE_ZERO; worker.next_bit_mode = MODE_ZERO;
@ -175,6 +212,8 @@ struct SetundefPass : public Pass {
} }
extra_args(args, argidx, design); extra_args(args, argidx, design);
if (expose_mode && !undriven_mode)
log_cmd_error("Option -expose must be used with option -undriven.\n");
if (!got_value) if (!got_value)
log_cmd_error("One of the options -zero, -one, -anyseq, -anyconst, or -random <seed> must be specified.\n"); log_cmd_error("One of the options -zero, -one, -anyseq, -anyconst, or -random <seed> must be specified.\n");
@ -188,33 +227,103 @@ struct SetundefPass : public Pass {
if (!module->processes.empty()) if (!module->processes.empty())
log_error("The 'setundef' command can't operate in -undriven mode on modules with processes. Run 'proc' first.\n"); log_error("The 'setundef' command can't operate in -undriven mode on modules with processes. Run 'proc' first.\n");
SigMap sigmap(module); if (expose_mode)
SigPool undriven_signals; {
SigMap sigmap(module);
dict<SigBit, bool> wire_drivers;
pool<SigBit> used_wires;
SigPool undriven_signals;
for (auto &it : module->wires_) for (auto cell : module->cells())
undriven_signals.add(sigmap(it.second)); for (auto &conn : cell->connections()) {
SigSpec sig = sigmap(conn.second);
if (cell->input(conn.first))
for (auto bit : sig)
if (bit.wire)
used_wires.insert(bit);
if (cell->output(conn.first))
for (int i = 0; i < GetSize(sig); i++)
if (sig[i].wire)
wire_drivers[sig[i]] = true;
}
for (auto &it : module->wires_) for (auto wire : module->wires()) {
if (it.second->port_input) if (wire->port_input) {
undriven_signals.del(sigmap(it.second)); SigSpec sig = sigmap(wire);
for (int i = 0; i < GetSize(sig); i++)
wire_drivers[sig[i]] = true;
}
if (wire->port_output) {
SigSpec sig = sigmap(wire);
for (auto bit : sig)
if (bit.wire)
used_wires.insert(bit);
}
}
CellTypes ct(design); pool<RTLIL::Wire*> undriven_wires;
for (auto &it : module->cells_) for (auto bit : used_wires)
for (auto &conn : it.second->connections()) if (!wire_drivers.count(bit))
if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first)) undriven_wires.insert(bit.wire);
undriven_signals.del(sigmap(conn.second));
RTLIL::SigSpec sig = undriven_signals.export_all(); for (auto &it : undriven_wires)
for (auto &c : sig.chunks()) { undriven_signals.add(sigmap(it));
RTLIL::SigSpec bits;
if (worker.next_bit_mode == MODE_ANYSEQ) for (auto &it : undriven_wires)
bits = module->Anyseq(NEW_ID, c.width); if (it->port_input)
else if (worker.next_bit_mode == MODE_ANYCONST) undriven_signals.del(sigmap(it));
bits = module->Anyconst(NEW_ID, c.width);
else CellTypes ct(design);
for (int i = 0; i < c.width; i++) for (auto &it : module->cells_)
bits.append(worker.next_bit()); for (auto &conn : it.second->connections())
module->connect(RTLIL::SigSig(c, bits)); if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first))
undriven_signals.del(sigmap(conn.second));
RTLIL::SigSpec sig = undriven_signals.export_all();
for (auto &c : sig.chunks()) {
RTLIL::Wire * wire;
if (c.wire->width == c.width) {
wire = c.wire;
wire->port_input = true;
} else {
string name = c.wire->name.str() + "$[" + std::to_string(c.width + c.offset) + ":" + std::to_string(c.offset) + "]";
wire = add_wire(module, name, c.width, true, false);
module->connect(RTLIL::SigSig(c, wire));
}
log("Exposing undriven wire %s as input.\n", wire->name.c_str());
}
module->fixup_ports();
}
else
{
SigMap sigmap(module);
SigPool undriven_signals;
for (auto &it : module->wires_)
undriven_signals.add(sigmap(it.second));
for (auto &it : module->wires_)
if (it.second->port_input)
undriven_signals.del(sigmap(it.second));
CellTypes ct(design);
for (auto &it : module->cells_)
for (auto &conn : it.second->connections())
if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first))
undriven_signals.del(sigmap(conn.second));
RTLIL::SigSpec sig = undriven_signals.export_all();
for (auto &c : sig.chunks()) {
RTLIL::SigSpec bits;
if (worker.next_bit_mode == MODE_ANYSEQ)
bits = module->Anyseq(NEW_ID, c.width);
else if (worker.next_bit_mode == MODE_ANYCONST)
bits = module->Anyconst(NEW_ID, c.width);
else
for (int i = 0; i < c.width; i++)
bits.append(worker.next_bit());
module->connect(RTLIL::SigSig(c, bits));
}
} }
} }

27
passes/cmds/show.cc
View File

@ -573,7 +573,7 @@ struct ShowWorker
struct ShowPass : public Pass { struct ShowPass : public Pass {
ShowPass() : Pass("show", "generate schematics using graphviz") { } ShowPass() : Pass("show", "generate schematics using graphviz") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -584,6 +584,7 @@ struct ShowPass : public Pass {
log("\n"); log("\n");
log(" -viewer <viewer>\n"); log(" -viewer <viewer>\n");
log(" Run the specified command with the graphics file as parameter.\n"); log(" Run the specified command with the graphics file as parameter.\n");
log(" On Windows, this pauses yosys until the viewer exits.\n");
log("\n"); log("\n");
log(" -format <format>\n"); log(" -format <format>\n");
log(" Generate a graphics file in the specified format. Use 'dot' to just\n"); log(" Generate a graphics file in the specified format. Use 'dot' to just\n");
@ -645,7 +646,7 @@ struct ShowPass : public Pass {
log(" do not add the module name as graph title to the dot file\n"); log(" do not add the module name as graph title to the dot file\n");
log("\n"); log("\n");
log("When no <format> is specified, 'dot' is used. When no <format> and <viewer> is\n"); log("When no <format> is specified, 'dot' is used. When no <format> and <viewer> is\n");
log("specified, 'xdot' is used to display the schematic.\n"); log("specified, 'xdot' is used to display the schematic (POSIX systems only).\n");
log("\n"); log("\n");
log("The generated output files are '~/.yosys_show.dot' and '~/.yosys_show.<format>',\n"); log("The generated output files are '~/.yosys_show.dot' and '~/.yosys_show.<format>',\n");
log("unless another prefix is specified using -prefix <prefix>.\n"); log("unless another prefix is specified using -prefix <prefix>.\n");
@ -655,7 +656,7 @@ struct ShowPass : public Pass {
log("the 'show' command is executed.\n"); log("the 'show' command is executed.\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
log_header(design, "Generating Graphviz representation of design.\n"); log_header(design, "Generating Graphviz representation of design.\n");
log_push(); log_push();
@ -817,14 +818,30 @@ struct ShowPass : public Pass {
log_cmd_error("Nothing there to show.\n"); log_cmd_error("Nothing there to show.\n");
if (format != "dot" && !format.empty()) { if (format != "dot" && !format.empty()) {
std::string cmd = stringf("dot -T%s '%s' > '%s.new' && mv '%s.new' '%s'", format.c_str(), dot_file.c_str(), out_file.c_str(), out_file.c_str(), out_file.c_str()); #ifdef _WIN32
// system()/cmd.exe does not understand single quotes on Windows.
#define DOT_CMD "dot -T%s \"%s\" > \"%s.new\" && move \"%s.new\" \"%s\""
#else
#define DOT_CMD "dot -T%s '%s' > '%s.new' && mv '%s.new' '%s'"
#endif
std::string cmd = stringf(DOT_CMD, format.c_str(), dot_file.c_str(), out_file.c_str(), out_file.c_str(), out_file.c_str());
#undef DOT_CMD
log("Exec: %s\n", cmd.c_str()); log("Exec: %s\n", cmd.c_str());
if (run_command(cmd) != 0) if (run_command(cmd) != 0)
log_cmd_error("Shell command failed!\n"); log_cmd_error("Shell command failed!\n");
} }
if (!viewer_exe.empty()) { if (!viewer_exe.empty()) {
std::string cmd = stringf("%s '%s' &", viewer_exe.c_str(), out_file.c_str()); #ifdef _WIN32
// system()/cmd.exe does not understand single quotes nor
// background tasks on Windows. So we have to pause yosys
// until the viewer exits.
#define VIEW_CMD "%s \"%s\""
#else
#define VIEW_CMD "%s '%s' &"
#endif
std::string cmd = stringf(VIEW_CMD, viewer_exe.c_str(), out_file.c_str());
#undef VIEW_CMD
log("Exec: %s\n", cmd.c_str()); log("Exec: %s\n", cmd.c_str());
if (run_command(cmd) != 0) if (run_command(cmd) != 0)
log_cmd_error("Shell command failed!\n"); log_cmd_error("Shell command failed!\n");

4
passes/cmds/splice.cc
View File

@ -247,7 +247,7 @@ struct SpliceWorker
struct SplicePass : public Pass { struct SplicePass : public Pass {
SplicePass() : Pass("splice", "create explicit splicing cells") { } SplicePass() : Pass("splice", "create explicit splicing cells") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -288,7 +288,7 @@ struct SplicePass : public Pass {
log("by selected wires are rewired.\n"); log("by selected wires are rewired.\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
bool sel_by_cell = false; bool sel_by_cell = false;
bool sel_by_wire = false; bool sel_by_wire = false;

4
passes/cmds/splitnets.cc
View File

@ -87,7 +87,7 @@ struct SplitnetsWorker
struct SplitnetsPass : public Pass { struct SplitnetsPass : public Pass {
SplitnetsPass() : Pass("splitnets", "split up multi-bit nets") { } SplitnetsPass() : Pass("splitnets", "split up multi-bit nets") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -109,7 +109,7 @@ struct SplitnetsPass : public Pass {
log(" and split nets so that no driver drives only part of a net.\n"); log(" and split nets so that no driver drives only part of a net.\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
bool flag_ports = false; bool flag_ports = false;
bool flag_driver = false; bool flag_driver = false;

4
passes/cmds/stat.cc
View File

@ -209,7 +209,7 @@ void read_liberty_cellarea(dict<IdString, double> &cell_area, string liberty_fil
struct StatPass : public Pass { struct StatPass : public Pass {
StatPass() : Pass("stat", "print some statistics") { } StatPass() : Pass("stat", "print some statistics") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -231,7 +231,7 @@ struct StatPass : public Pass {
log(" e.g. $add_8 for an 8 bit wide $add cell.\n"); log(" e.g. $add_8 for an 8 bit wide $add cell.\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
log_header(design, "Printing statistics.\n"); log_header(design, "Printing statistics.\n");

4
passes/cmds/tee.cc
View File

@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN
struct TeePass : public Pass { struct TeePass : public Pass {
TeePass() : Pass("tee", "redirect command output to file") { } TeePass() : Pass("tee", "redirect command output to file") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -49,7 +49,7 @@ struct TeePass : public Pass {
log(" Add/subract INT from the -v setting for this command.\n"); log(" Add/subract INT from the -v setting for this command.\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
std::vector<FILE*> backup_log_files, files_to_close; std::vector<FILE*> backup_log_files, files_to_close;
int backup_log_verbose_level = log_verbose_level; int backup_log_verbose_level = log_verbose_level;

4
passes/cmds/torder.cc
View File

@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN
struct TorderPass : public Pass { struct TorderPass : public Pass {
TorderPass() : Pass("torder", "print cells in topological order") { } TorderPass() : Pass("torder", "print cells in topological order") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -43,7 +43,7 @@ struct TorderPass : public Pass {
log(" are not used in topological sorting. this option deactivates that.\n"); log(" are not used in topological sorting. this option deactivates that.\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
bool noautostop = false; bool noautostop = false;
dict<IdString, pool<IdString>> stop_db; dict<IdString, pool<IdString>> stop_db;

17
passes/cmds/trace.cc
View File

@ -25,34 +25,34 @@ PRIVATE_NAMESPACE_BEGIN
struct TraceMonitor : public RTLIL::Monitor struct TraceMonitor : public RTLIL::Monitor
{ {
virtual void notify_module_add(RTLIL::Module *module) YS_OVERRIDE void notify_module_add(RTLIL::Module *module) YS_OVERRIDE
{ {
log("#TRACE# Module add: %s\n", log_id(module)); log("#TRACE# Module add: %s\n", log_id(module));
} }
virtual void notify_module_del(RTLIL::Module *module) YS_OVERRIDE void notify_module_del(RTLIL::Module *module) YS_OVERRIDE
{ {
log("#TRACE# Module delete: %s\n", log_id(module)); log("#TRACE# Module delete: %s\n", log_id(module));
} }
virtual void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, RTLIL::SigSpec &sig) YS_OVERRIDE void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, RTLIL::SigSpec &sig) YS_OVERRIDE
{ {
log("#TRACE# Cell connect: %s.%s.%s = %s (was: %s)\n", log_id(cell->module), log_id(cell), log_id(port), log_signal(sig), log_signal(old_sig)); log("#TRACE# Cell connect: %s.%s.%s = %s (was: %s)\n", log_id(cell->module), log_id(cell), log_id(port), log_signal(sig), log_signal(old_sig));
} }
virtual void notify_connect(RTLIL::Module *module, const RTLIL::SigSig &sigsig) YS_OVERRIDE void notify_connect(RTLIL::Module *module, const RTLIL::SigSig &sigsig) YS_OVERRIDE
{ {
log("#TRACE# Connection in module %s: %s = %s\n", log_id(module), log_signal(sigsig.first), log_signal(sigsig.second)); log("#TRACE# Connection in module %s: %s = %s\n", log_id(module), log_signal(sigsig.first), log_signal(sigsig.second));
} }
virtual void notify_connect(RTLIL::Module *module, const std::vector<RTLIL::SigSig> &sigsig_vec) YS_OVERRIDE void notify_connect(RTLIL::Module *module, const std::vector<RTLIL::SigSig> &sigsig_vec) YS_OVERRIDE
{ {
log("#TRACE# New connections in module %s:\n", log_id(module)); log("#TRACE# New connections in module %s:\n", log_id(module));
for (auto &sigsig : sigsig_vec) for (auto &sigsig : sigsig_vec)
log("## %s = %s\n", log_signal(sigsig.first), log_signal(sigsig.second)); log("## %s = %s\n", log_signal(sigsig.first), log_signal(sigsig.second));
} }
virtual void notify_blackout(RTLIL::Module *module) YS_OVERRIDE void notify_blackout(RTLIL::Module *module) YS_OVERRIDE
{ {
log("#TRACE# Blackout in module %s:\n", log_id(module)); log("#TRACE# Blackout in module %s:\n", log_id(module));
} }
@ -60,7 +60,7 @@ struct TraceMonitor : public RTLIL::Monitor
struct TracePass : public Pass { struct TracePass : public Pass {
TracePass() : Pass("trace", "redirect command output to file") { } TracePass() : Pass("trace", "redirect command output to file") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -70,7 +70,7 @@ struct TracePass : public Pass {
log("the design in real time.\n"); log("the design in real time.\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
size_t argidx; size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) for (argidx = 1; argidx < args.size(); argidx++)
@ -95,4 +95,3 @@ struct TracePass : public Pass {
} TracePass; } TracePass;
PRIVATE_NAMESPACE_END PRIVATE_NAMESPACE_END

4
passes/cmds/write_file.cc
View File

@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
struct WriteFileFrontend : public Frontend { struct WriteFileFrontend : public Frontend {
WriteFileFrontend() : Frontend("=write_file", "write a text to a file") { } WriteFileFrontend() : Frontend("=write_file", "write a text to a file") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -44,7 +44,7 @@ struct WriteFileFrontend : public Frontend {
log(" EOT\n"); log(" EOT\n");
log("\n"); log("\n");
} }
virtual void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design*) void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design*) YS_OVERRIDE
{ {
bool append_mode = false; bool append_mode = false;
std::string output_filename; std::string output_filename;

4
passes/equiv/equiv_add.cc
View File

@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
struct EquivAddPass : public Pass { struct EquivAddPass : public Pass {
EquivAddPass() : Pass("equiv_add", "add a $equiv cell") { } EquivAddPass() : Pass("equiv_add", "add a $equiv cell") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -39,7 +39,7 @@ struct EquivAddPass : public Pass {
log("This command adds $equiv cells for the ports of the specified cells.\n"); log("This command adds $equiv cells for the ports of the specified cells.\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, Design *design) void execute(std::vector<std::string> args, Design *design) YS_OVERRIDE
{ {
bool try_mode = false; bool try_mode = false;

4
passes/equiv/equiv_induct.cc
View File

@ -162,7 +162,7 @@ struct EquivInductWorker
struct EquivInductPass : public Pass { struct EquivInductPass : public Pass {
EquivInductPass() : Pass("equiv_induct", "proving $equiv cells using temporal induction") { } EquivInductPass() : Pass("equiv_induct", "proving $equiv cells using temporal induction") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -192,7 +192,7 @@ struct EquivInductPass : public Pass {
log("after reset.\n"); log("after reset.\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, Design *design) void execute(std::vector<std::string> args, Design *design) YS_OVERRIDE
{ {
int success_counter = 0; int success_counter = 0;
bool model_undef = false; bool model_undef = false;

4
passes/equiv/equiv_make.cc
View File

@ -390,7 +390,7 @@ struct EquivMakeWorker
struct EquivMakePass : public Pass { struct EquivMakePass : public Pass {
EquivMakePass() : Pass("equiv_make", "prepare a circuit for equivalence checking") { } EquivMakePass() : Pass("equiv_make", "prepare a circuit for equivalence checking") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -415,7 +415,7 @@ struct EquivMakePass : public Pass {
log("checking problem. Use 'miter -equiv' if you want to create a miter circuit.\n"); log("checking problem. Use 'miter -equiv' if you want to create a miter circuit.\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
EquivMakeWorker worker; EquivMakeWorker worker;
worker.ct.setup(design); worker.ct.setup(design);

4
passes/equiv/equiv_mark.cc
View File

@ -204,7 +204,7 @@ struct EquivMarkWorker
struct EquivMarkPass : public Pass { struct EquivMarkPass : public Pass {
EquivMarkPass() : Pass("equiv_mark", "mark equivalence checking regions") { } EquivMarkPass() : Pass("equiv_mark", "mark equivalence checking regions") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -216,7 +216,7 @@ struct EquivMarkPass : public Pass {
log("wires and cells.\n"); log("wires and cells.\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, Design *design) void execute(std::vector<std::string> args, Design *design) YS_OVERRIDE
{ {
log_header(design, "Executing EQUIV_MARK pass.\n"); log_header(design, "Executing EQUIV_MARK pass.\n");

4
passes/equiv/equiv_miter.cc
View File

@ -261,7 +261,7 @@ struct EquivMiterWorker
struct EquivMiterPass : public Pass { struct EquivMiterPass : public Pass {
EquivMiterPass() : Pass("equiv_miter", "extract miter from equiv circuit") { } EquivMiterPass() : Pass("equiv_miter", "extract miter from equiv circuit") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -282,7 +282,7 @@ struct EquivMiterPass : public Pass {
log(" Create compare logic that handles undefs correctly\n"); log(" Create compare logic that handles undefs correctly\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
EquivMiterWorker worker; EquivMiterWorker worker;
worker.ct.setup(design); worker.ct.setup(design);

4
passes/equiv/equiv_purge.cc
View File

@ -176,7 +176,7 @@ struct EquivPurgeWorker
struct EquivPurgePass : public Pass { struct EquivPurgePass : public Pass {
EquivPurgePass() : Pass("equiv_purge", "purge equivalence checking module") { } EquivPurgePass() : Pass("equiv_purge", "purge equivalence checking module") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -187,7 +187,7 @@ struct EquivPurgePass : public Pass {
log("ports as needed.\n"); log("ports as needed.\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, Design *design) void execute(std::vector<std::string> args, Design *design) YS_OVERRIDE
{ {
log_header(design, "Executing EQUIV_PURGE pass.\n"); log_header(design, "Executing EQUIV_PURGE pass.\n");

4
passes/equiv/equiv_remove.cc
View File

@ -24,7 +24,7 @@ PRIVATE_NAMESPACE_BEGIN
struct EquivRemovePass : public Pass { struct EquivRemovePass : public Pass {
EquivRemovePass() : Pass("equiv_remove", "remove $equiv cells") { } EquivRemovePass() : Pass("equiv_remove", "remove $equiv cells") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -40,7 +40,7 @@ struct EquivRemovePass : public Pass {
log(" keep gate circuit\n"); log(" keep gate circuit\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, Design *design) void execute(std::vector<std::string> args, Design *design) YS_OVERRIDE
{ {
bool mode_gold = false; bool mode_gold = false;
bool mode_gate = false; bool mode_gate = false;

4
passes/equiv/equiv_simple.cc
View File

@ -273,7 +273,7 @@ struct EquivSimpleWorker
struct EquivSimplePass : public Pass { struct EquivSimplePass : public Pass {
EquivSimplePass() : Pass("equiv_simple", "try proving simple $equiv instances") { } EquivSimplePass() : Pass("equiv_simple", "try proving simple $equiv instances") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -298,7 +298,7 @@ struct EquivSimplePass : public Pass {
log(" the max. number of time steps to be considered (default = 1)\n"); log(" the max. number of time steps to be considered (default = 1)\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, Design *design) void execute(std::vector<std::string> args, Design *design) YS_OVERRIDE
{ {
bool verbose = false, short_cones = false, model_undef = false, nogroup = false; bool verbose = false, short_cones = false, model_undef = false, nogroup = false;
int success_counter = 0; int success_counter = 0;

4
passes/equiv/equiv_status.cc
View File

@ -24,7 +24,7 @@ PRIVATE_NAMESPACE_BEGIN
struct EquivStatusPass : public Pass { struct EquivStatusPass : public Pass {
EquivStatusPass() : Pass("equiv_status", "print status of equivalent checking module") { } EquivStatusPass() : Pass("equiv_status", "print status of equivalent checking module") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -36,7 +36,7 @@ struct EquivStatusPass : public Pass {
log(" produce an error if any unproven $equiv cell is found\n"); log(" produce an error if any unproven $equiv cell is found\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, Design *design) void execute(std::vector<std::string> args, Design *design) YS_OVERRIDE
{ {
bool assert_mode = false; bool assert_mode = false;
int unproven_count = 0; int unproven_count = 0;

4
passes/equiv/equiv_struct.cc
View File

@ -283,7 +283,7 @@ struct EquivStructWorker
struct EquivStructPass : public Pass { struct EquivStructPass : public Pass {
EquivStructPass() : Pass("equiv_struct", "structural equivalence checking") { } EquivStructPass() : Pass("equiv_struct", "structural equivalence checking") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -314,7 +314,7 @@ struct EquivStructPass : public Pass {
log(" maximum number of iterations to run before aborting\n"); log(" maximum number of iterations to run before aborting\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, Design *design) void execute(std::vector<std::string> args, Design *design) YS_OVERRIDE
{ {
pool<IdString> fwonly_cells({ "$equiv" }); pool<IdString> fwonly_cells({ "$equiv" });
bool mode_icells = false; bool mode_icells = false;

4
passes/fsm/fsm.cc
View File

@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN
struct FsmPass : public Pass { struct FsmPass : public Pass {
FsmPass() : Pass("fsm", "extract and optimize finite state machines") { } FsmPass() : Pass("fsm", "extract and optimize finite state machines") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -68,7 +68,7 @@ struct FsmPass : public Pass {
log(" passed through to fsm_recode pass\n"); log(" passed through to fsm_recode pass\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
bool flag_nomap = false; bool flag_nomap = false;
bool flag_norecode = false; bool flag_norecode = false;

4
passes/fsm/fsm_detect.cc
View File

@ -245,7 +245,7 @@ static void detect_fsm(RTLIL::Wire *wire)
struct FsmDetectPass : public Pass { struct FsmDetectPass : public Pass {
FsmDetectPass() : Pass("fsm_detect", "finding FSMs in design") { } FsmDetectPass() : Pass("fsm_detect", "finding FSMs in design") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -261,7 +261,7 @@ struct FsmDetectPass : public Pass {
log("'fsm_encoding' attribute to \"none\".\n"); log("'fsm_encoding' attribute to \"none\".\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
log_header(design, "Executing FSM_DETECT pass (finding FSMs in design).\n"); log_header(design, "Executing FSM_DETECT pass (finding FSMs in design).\n");
extra_args(args, 1, design); extra_args(args, 1, design);

4
passes/fsm/fsm_expand.cc
View File

@ -265,7 +265,7 @@ struct FsmExpand
struct FsmExpandPass : public Pass { struct FsmExpandPass : public Pass {
FsmExpandPass() : Pass("fsm_expand", "expand FSM cells by merging logic into it") { } FsmExpandPass() : Pass("fsm_expand", "expand FSM cells by merging logic into it") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -279,7 +279,7 @@ struct FsmExpandPass : public Pass {
log("word-wide cells. Call with -full to consider all cells for merging.\n"); log("word-wide cells. Call with -full to consider all cells for merging.\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
bool full_mode = false; bool full_mode = false;

4
passes/fsm/fsm_export.cc
View File

@ -120,7 +120,7 @@ void write_kiss2(struct RTLIL::Module *module, struct RTLIL::Cell *cell, std::st
*/ */
struct FsmExportPass : public Pass { struct FsmExportPass : public Pass {
FsmExportPass() : Pass("fsm_export", "exporting FSMs to KISS2 files") { } FsmExportPass() : Pass("fsm_export", "exporting FSMs to KISS2 files") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -143,7 +143,7 @@ struct FsmExportPass : public Pass {
log(" use binary state encoding as state names instead of s0, s1, ...\n"); log(" use binary state encoding as state names instead of s0, s1, ...\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
dict<RTLIL::IdString, RTLIL::Const>::iterator attr_it; dict<RTLIL::IdString, RTLIL::Const>::iterator attr_it;
std::string arg; std::string arg;

4
passes/fsm/fsm_extract.cc
View File

@ -401,7 +401,7 @@ static void extract_fsm(RTLIL::Wire *wire)
struct FsmExtractPass : public Pass { struct FsmExtractPass : public Pass {
FsmExtractPass() : Pass("fsm_extract", "extracting FSMs in design") { } FsmExtractPass() : Pass("fsm_extract", "extracting FSMs in design") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -417,7 +417,7 @@ struct FsmExtractPass : public Pass {
log("'opt_clean' pass to eliminate this signal.\n"); log("'opt_clean' pass to eliminate this signal.\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
log_header(design, "Executing FSM_EXTRACT pass (extracting FSM from design).\n"); log_header(design, "Executing FSM_EXTRACT pass (extracting FSM from design).\n");
extra_args(args, 1, design); extra_args(args, 1, design);

4
passes/fsm/fsm_info.cc
View File

@ -30,7 +30,7 @@ PRIVATE_NAMESPACE_BEGIN
struct FsmInfoPass : public Pass { struct FsmInfoPass : public Pass {
FsmInfoPass() : Pass("fsm_info", "print information on finite state machines") { } FsmInfoPass() : Pass("fsm_info", "print information on finite state machines") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -41,7 +41,7 @@ struct FsmInfoPass : public Pass {
log("pass so that this information is included in the synthesis log file.\n"); log("pass so that this information is included in the synthesis log file.\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
log_header(design, "Executing FSM_INFO pass (dumping all available information on FSM cells).\n"); log_header(design, "Executing FSM_INFO pass (dumping all available information on FSM cells).\n");
extra_args(args, 1, design); extra_args(args, 1, design);

4
passes/fsm/fsm_map.cc
View File

@ -322,7 +322,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
struct FsmMapPass : public Pass { struct FsmMapPass : public Pass {
FsmMapPass() : Pass("fsm_map", "mapping FSMs to basic logic") { } FsmMapPass() : Pass("fsm_map", "mapping FSMs to basic logic") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -331,7 +331,7 @@ struct FsmMapPass : public Pass {
log("This pass translates FSM cells to flip-flops and logic.\n"); log("This pass translates FSM cells to flip-flops and logic.\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
log_header(design, "Executing FSM_MAP pass (mapping FSMs to basic logic).\n"); log_header(design, "Executing FSM_MAP pass (mapping FSMs to basic logic).\n");
extra_args(args, 1, design); extra_args(args, 1, design);

4
passes/fsm/fsm_opt.cc
View File

@ -323,7 +323,7 @@ PRIVATE_NAMESPACE_BEGIN
struct FsmOptPass : public Pass { struct FsmOptPass : public Pass {
FsmOptPass() : Pass("fsm_opt", "optimize finite state machines") { } FsmOptPass() : Pass("fsm_opt", "optimize finite state machines") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -334,7 +334,7 @@ struct FsmOptPass : public Pass {
log("combination with the 'opt_clean' pass (see also 'help fsm').\n"); log("combination with the 'opt_clean' pass (see also 'help fsm').\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
log_header(design, "Executing FSM_OPT pass (simple optimizations of FSMs).\n"); log_header(design, "Executing FSM_OPT pass (simple optimizations of FSMs).\n");
extra_args(args, 1, design); extra_args(args, 1, design);

4
passes/fsm/fsm_recode.cc
View File

@ -126,7 +126,7 @@ static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fs
struct FsmRecodePass : public Pass { struct FsmRecodePass : public Pass {
FsmRecodePass() : Pass("fsm_recode", "recoding finite state machines") { } FsmRecodePass() : Pass("fsm_recode", "recoding finite state machines") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -151,7 +151,7 @@ struct FsmRecodePass : public Pass {
log(" .map <old_bitpattern> <new_bitpattern>\n"); log(" .map <old_bitpattern> <new_bitpattern>\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
FILE *fm_set_fsm_file = NULL; FILE *fm_set_fsm_file = NULL;
FILE *encfile = NULL; FILE *encfile = NULL;

4
passes/hierarchy/hierarchy.cc
View File

@ -343,7 +343,7 @@ int find_top_mod_score(Design *design, Module *module, dict<Module*, int> &db)
struct HierarchyPass : public Pass { struct HierarchyPass : public Pass {
HierarchyPass() : Pass("hierarchy", "check, expand and clean up design hierarchy") { } HierarchyPass() : Pass("hierarchy", "check, expand and clean up design hierarchy") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -414,7 +414,7 @@ struct HierarchyPass : public Pass {
log("in the current design.\n"); log("in the current design.\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
log_header(design, "Executing HIERARCHY pass (managing design hierarchy).\n"); log_header(design, "Executing HIERARCHY pass (managing design hierarchy).\n");

4
passes/hierarchy/submod.cc
View File

@ -269,7 +269,7 @@ struct SubmodWorker
struct SubmodPass : public Pass { struct SubmodPass : public Pass {
SubmodPass() : Pass("submod", "moving part of a module to a new submodule") { } SubmodPass() : Pass("submod", "moving part of a module to a new submodule") { }
virtual void help() void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
@ -297,7 +297,7 @@ struct SubmodPass : public Pass {
log("with -copy to not modify the source module.\n"); log("with -copy to not modify the source module.\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
log_header(design, "Executing SUBMOD pass (moving cells to submodules as requested).\n"); log_header(design, "Executing SUBMOD pass (moving cells to submodules as requested).\n");
log_push(); log_push();

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