mirror of https://github.com/YosysHQ/yosys.git
Cleanup
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c663a3680b
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29d446d758
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@ -398,10 +398,8 @@ endmatch
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code argQ argD
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{
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if (clock != SigBit()) {
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if (port(ff, \CLK) != clock)
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if (clock != SigBit() && port(ff, \CLK) != clock)
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reject;
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}
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SigSpec Q = port(ff, \Q);
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if (ffoffset + GetSize(argQ) > GetSize(Q))
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@ -580,10 +578,8 @@ endmatch
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code argQ
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if (ff) {
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if (clock != SigBit()) {
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if (port(ff, \CLK) != clock)
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if (clock != SigBit() && port(ff, \CLK) != clock)
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reject;
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}
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SigSpec D = port(ff, \D);
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if (ffoffset + GetSize(argD) > GetSize(D))
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