riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

undo formatting fuckup

This commit is contained in:
Pepijn de Vos 2019-10-28 12:57:12 +01:00
parent f88335a8a5
commit 293b2c2de5
1 changed files with 25 additions and 25 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

50
techlibs/gowin/synth_gowin.cc
View File

@ -33,42 +33,42 @@ struct SynthGowinPass : public ScriptPass
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
log(" synth_gowin [options]\n"); log(" synth_gowin [options]\n");
log("\n"); log("\n");
log("This command runs synthesis for Gowin FPGAs. This work is experimental.\n"); log("This command runs synthesis for Gowin FPGAs. This work is experimental.\n");
log("\n"); log("\n");
log(" -top <module>\n"); log(" -top <module>\n");
log(" use the specified module as top module (default='top')\n"); log(" use the specified module as top module (default='top')\n");
log("\n"); log("\n");
log(" -vout <file>\n"); log(" -vout <file>\n");
log(" write the design to the specified Verilog netlist file. writing of an\n"); log(" write the design to the specified Verilog netlist file. writing of an\n");
log(" output file is omitted if this parameter is not specified.\n"); log(" output file is omitted if this parameter is not specified.\n");
log("\n"); log("\n");
log(" -run <from_label>:<to_label>\n"); log(" -run <from_label>:<to_label>\n");
log(" only run the commands between the labels (see below). an empty\n"); log(" only run the commands between the labels (see below). an empty\n");
log(" from label is synonymous to 'begin', and empty to label is\n"); log(" from label is synonymous to 'begin', and empty to label is\n");
log(" synonymous to the end of the command list.\n"); log(" synonymous to the end of the command list.\n");
log("\n"); log("\n");
log(" -nodffe\n"); log(" -nodffe\n");
log(" do not use flipflops with CE in output netlist\n"); log(" do not use flipflops with CE in output netlist\n");
log("\n"); log("\n");
log(" -nobram\n"); log(" -nobram\n");
log(" do not use BRAM cells in output netlist\n"); log(" do not use BRAM cells in output netlist\n");
log("\n"); log("\n");
log(" -nodram\n"); log(" -nodram\n");
log(" do not use distributed RAM cells in output netlist\n"); log(" do not use distributed RAM cells in output netlist\n");
log("\n"); log("\n");
log(" -noflatten\n"); log(" -noflatten\n");
log(" do not flatten design before synthesis\n"); log(" do not flatten design before synthesis\n");
log("\n"); log("\n");
log(" -retime\n"); log(" -retime\n");
log(" run 'abc' with -dff option\n"); log(" run 'abc' with -dff option\n");
log("\n"); log("\n");
log(" -nowidelut\n"); log(" -nowidelut\n");
log(" do not use muxes to implement LUTs larger than LUT4s\n"); log(" do not use muxes to implement LUTs larger than LUT4s\n");
log("\n"); log("\n");
log(" -abc9\n"); log(" -abc9\n");
log(" use new ABC9 flow (EXPERIMENTAL)\n"); log(" use new ABC9 flow (EXPERIMENTAL)\n");
log("\n"); log("\n");
log("\n"); log("\n");
log("The following commands are executed by this synthesis command:\n"); log("The following commands are executed by this synthesis command:\n");
@ -237,7 +237,7 @@ struct SynthGowinPass : public ScriptPass
run("setundef -undriven -params -zero"); run("setundef -undriven -params -zero");
run("hilomap -singleton -hicell VCC V -locell GND G"); run("hilomap -singleton -hicell VCC V -locell GND G");
run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O", "(unless -noiopads)"); run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O", "(unless -noiopads)");
run("dffinit -ff DFF Q INIT"); run("dffinit -ff DFF Q INIT");
run("clean"); run("clean");
} }