Moved common techlib files to techlibs/common

Makefile

@@ -73,7 +73,7 @@ endif
 include frontends/*/Makefile.inc
 include passes/*/Makefile.inc
 include backends/*/Makefile.inc
-include techlibs/Makefile.inc
+include techlibs/*/Makefile.inc
 
 top-all: $(TARGETS) $(EXTRA_TARGETS)
 

manual/CHAPTER_CellLib.tex

@@ -22,7 +22,7 @@ Note that all RTL cells have parameters indicating the size of inputs and output
 passes modify RTL cells they must always keep the values of these parameters in sync with
 the size of the signals connected to the inputs and outputs.
 
-Simulation models for the RTL cells can be found in the file {\tt techlibs/simlib.v} in the Yosys
+Simulation models for the RTL cells can be found in the file {\tt techlibs/common/simlib.v} in the Yosys
 source tree.
 
 \subsection{Unary Operators}
@@ -347,7 +347,7 @@ Add a brief description of the {\tt \$fsm} cell type.
 For gate level logic networks, fixed function single bit cells are used that do
 not provide any parameters.
 
-Simulation models for these cells can be found in the file {\tt techlibs/stdcells\_sim.v} in the Yosys
+Simulation models for these cells can be found in the file {\tt techlibs/common/stdcells\_sim.v} in the Yosys
 source tree.
 
 \begin{table}[t]

manual/CHAPTER_Techmap.tex

@@ -27,7 +27,7 @@ cells with the provided implementation.
 
 When no map file is provided, {\tt techmap} uses a built-in map file that
 maps the Yosys RTL cell types to the internal gate library used by Yosys.
-The curious reader may find this map file as {\tt techlibs/stdcells.v} in
+The curious reader may find this map file as {\tt techlibs/common/stdcells.v} in
 the Yosys source tree.
 
 Additional features have been added to {\tt techmap} to allow for conditional

passes/techmap/Makefile.inc

@@ -2,7 +2,7 @@
 GENFILES += passes/techmap/stdcells.inc
 OBJS += passes/techmap/techmap.o
 
-passes/techmap/stdcells.inc: techlibs/stdcells.v
+passes/techmap/stdcells.inc: techlibs/common/stdcells.v
 	echo "// autogenerated from $<" > $@.new
 	od -v -td1 -w1 $< | awk 'BEGIN { print "static char stdcells_code[] = {"; } $$2 != "" { print $$2 ","; } \
 			END { print 0 "};"; }' | fmt >> $@.new

techlibs/Makefile.inc

@@ -1,7 +0,0 @@
-
-EXTRA_TARGETS += techlibs/blackbox.v
-
-techlibs/blackbox.v: techlibs/blackbox.sed techlibs/simlib.v techlibs/stdcells_sim.v
-	cat techlibs/simlib.v techlibs/stdcells_sim.v | sed -rf techlibs/blackbox.sed > techlibs/blackbox.v.new
-	mv techlibs/blackbox.v.new techlibs/blackbox.v
-

techlibs/common/Makefile.inc

@@ -0,0 +1,7 @@
+
+EXTRA_TARGETS += techlibs/common/blackbox.v
+
+techlibs/common/blackbox.v: techlibs/common/blackbox.sed techlibs/common/simlib.v techlibs/common/stdcells_sim.v
+	cat techlibs/common/simlib.v techlibs/common/stdcells_sim.v | sed -rf techlibs/common/blackbox.sed > techlibs/common/blackbox.v.new
+	mv techlibs/common/blackbox.v.new techlibs/common/blackbox.v
+

tests/i2c_bench/run-test.sh

@@ -27,8 +27,8 @@ EOT
 ./testbench_ref -tclbatch testbench_ref.tcl
 
 vlogcomp --work syn i2c_master_syn.v
-vlogcomp --work syn ../../techlibs/simlib.v
-vlogcomp --work syn ../../techlibs/stdcells_sim.v
+vlogcomp --work syn ../../techlibs/common/simlib.v
+vlogcomp --work syn ../../techlibs/common/stdcells_sim.v
 vlogcomp --work syn i2c_slave_model.v
 vlogcomp --work syn spi_slave_model.v
 vlogcomp --work syn tst_bench_top.v

tests/tools/autotest.sh

@@ -130,8 +130,8 @@ do
 			"$toolsdir"/../../yosys -b "verilog $backend_opts" "$@" -o ${bn}_syn${test_count}.v $fn $scriptfiles
 			compile_and_run ${bn}_tb_syn${test_count} ${bn}_out_syn${test_count} \
 					${bn}_tb.v ${bn}_syn${test_count}.v $libs \
-					"$toolsdir"/../../techlibs/simlib.v \
-					"$toolsdir"/../../techlibs/stdcells_sim.v
+					"$toolsdir"/../../techlibs/common/simlib.v \
+					"$toolsdir"/../../techlibs/common/stdcells_sim.v
 			if $genvcd; then mv testbench.vcd ${bn}_syn${test_count}.vcd; fi
 			$toolsdir/cmp_tbdata ${bn}_out_ref ${bn}_out_syn${test_count}
 			test_count=$(( test_count + 1 ))

tests/tools/rtlview.sh

@@ -11,7 +11,7 @@ prjdir="$(dirname $0)/rtlview.tmp"
 mkdir -p "$prjdir"
 
 cp "$1" "$prjdir"/schematic.v
-cp "$(dirname $0)"/../../techlibs/blackbox.v "$prjdir"/blackbox.v
+cp "$(dirname $0)"/../../techlibs/common/blackbox.v "$prjdir"/blackbox.v
 cd "$prjdir"
 
 if fuser -s ise.out; then