mirror of https://github.com/YosysHQ/yosys.git
Fixed handling of cell ports that aren't wires
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2877d5e504
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@ -90,6 +90,9 @@ struct OptRmportsPass : public Pass {
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for(int i=0; i<conn.second.size(); i++)
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for(int i=0; i<conn.second.size(); i++)
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{
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{
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auto sig = conn.second[i].wire;
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auto sig = conn.second[i].wire;
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if(sig == NULL)
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continue;
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//log(" sig %s\n", sig->name.c_str());
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//log(" sig %s\n", sig->name.c_str());
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if( (sig->port_input || sig->port_output) && (used_ports.find(sig->name) == used_ports.end()) )
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if( (sig->port_input || sig->port_output) && (used_ports.find(sig->name) == used_ports.end()) )
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used_ports.emplace(sig->name);
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used_ports.emplace(sig->name);
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