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Cleaned tests

This commit is contained in:
Miodrag Milanovic 2019-10-04 12:42:06 +02:00
parent f94dc2c072
commit 286a272872
5 changed files with 4 additions and 49 deletions
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18
tests/efinix/fsm.v
View File

@ -53,21 +53,3 @@
end end
endmodule endmodule
module top (
input clk,
input rst,
input a,
input b,
output g0,
output g1
);
fsm u_fsm ( .clock(clk),
.reset(rst),
.req_0(a),
.req_1(b),
.gnt_0(g0),
.gnt_1(g1));
endmodule

4
tests/efinix/fsm.ys
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@ -1,12 +1,12 @@
read_verilog fsm.v read_verilog fsm.v
hierarchy -top top hierarchy -top fsm
proc proc
flatten flatten
#ERROR: Found 4 unproven $equiv cells in 'equiv_status -assert'. #ERROR: Found 4 unproven $equiv cells in 'equiv_status -assert'.
#equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check #equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
equiv_opt -map +/efinix/cells_sim.v synth_efinix # equivalency check equiv_opt -map +/efinix/cells_sim.v synth_efinix # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module cd fsm # Constrain all select calls below inside the top module
select -assert-count 1 t:EFX_GBUFCE select -assert-count 1 t:EFX_GBUFCE
select -assert-count 6 t:EFX_FF select -assert-count 6 t:EFX_FF

6
tests/efinix/shifter.v
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@ -9,14 +9,8 @@ in
always @(posedge clk) always @(posedge clk)
begin begin
`ifndef BUG
out <= out >> 1;
out[7] <= in;
`else
out <= out << 1; out <= out << 1;
out[7] <= in; out[7] <= in;
`endif
end end
endmodule endmodule

21
tests/efinix/tribuf.v
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@ -2,28 +2,7 @@ module tristate (en, i, o);
input en; input en;
input i; input i;
output reg o; output reg o;
`ifndef BUG
always @(en or i) always @(en or i)
o <= (en)? i : 1'bZ; o <= (en)? i : 1'bZ;
`else
always @(en or i)
o <= (en)? ~i : 1'bZ;
`endif
endmodule
module top (
input en,
input a,
output b
);
tristate u_tri (
.en (en ),
.i (a ),
.o (b )
);
endmodule endmodule

4
tests/efinix/tribuf.ys
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@ -1,12 +1,12 @@
read_verilog tribuf.v read_verilog tribuf.v
hierarchy -top top hierarchy -top tristate
proc proc
tribuf tribuf
flatten flatten
synth synth
equiv_opt -assert -map +/efinix/cells_sim.v -map +/simcells.v synth_efinix # equivalency check equiv_opt -assert -map +/efinix/cells_sim.v -map +/simcells.v synth_efinix # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module cd tristate # Constrain all select calls below inside the top module
#Internal cell type used. Need support it. #Internal cell type used. Need support it.
select -assert-count 1 t:$_TBUF_ select -assert-count 1 t:$_TBUF_
select -assert-none t:$_TBUF_ %% t:* %D select -assert-none t:$_TBUF_ %% t:* %D