mirror of https://github.com/YosysHQ/yosys.git
SigSpec::extract to take negative lengths
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@ -3353,7 +3353,7 @@ RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
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{
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{
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unpack();
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unpack();
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cover("kernel.rtlil.sigspec.extract_pos");
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cover("kernel.rtlil.sigspec.extract_pos");
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return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
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return std::vector<RTLIL::SigBit>(bits_.begin() + offset, length >= 0 ? bits_.begin() + offset + length : bits_.end() + length + 1);
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}
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}
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void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
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void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
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