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verilog: default to input in sv mode if task/func has no dir ... 

otherwise error
This commit is contained in:
Eddie Hung 2020-05-13 13:33:37 -07:00
parent 0d2c33f9f4
commit 237962debd
1 changed files with 10 additions and 2 deletions
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12
frontends/verilog/verilog_parser.y
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@ -855,8 +855,16 @@ task_func_port:
frontend_verilog_yyerror("task/function argument range must be of the form: [<expr>:<expr>], [<expr>+:<expr>], or [<expr>-:<expr>]"); frontend_verilog_yyerror("task/function argument range must be of the form: [<expr>:<expr>], [<expr>+:<expr>], or [<expr>-:<expr>]");
} wire_name | } wire_name |
{ {
if (!astbuf1) if (!astbuf1) {
frontend_verilog_yyerror("Non-ANSI style task/function arguments not currently supported"); if (!sv_mode)
frontend_verilog_yyerror("task/function argument direction missing");
albuf = new dict<IdString, AstNode*>;
astbuf1 = new AstNode(AST_WIRE);
current_wire_rand = false;
current_wire_const = false;
astbuf1->is_input = true;
astbuf2 = NULL;
}
} wire_name; } wire_name;
task_func_body: task_func_body: