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Xilinx DRAMS: RAM64X1D, RAM128X1D

This commit is contained in:
Clifford Wolf 2015-04-09 13:37:07 +02:00
parent 25781e329b
commit 229825e1b8
3 changed files with 67 additions and 13 deletions
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23
techlibs/xilinx/drams.txt
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@ -1,7 +1,7 @@
bram $__XILINX_RAM32X1D bram $__XILINX_RAM64X1D
init 1 init 1
abits 5 abits 6
dbits 1 dbits 1
groups 2 groups 2
ports 1 1 ports 1 1
@ -12,6 +12,23 @@ bram $__XILINX_RAM32X1D
clkpol 0 2 clkpol 0 2
endbram endbram
match $__XILINX_RAM32X1D bram $__XILINX_RAM128X1D
init 1
abits 7
dbits 1
groups 2
ports 1 1
wrmode 0 1
enable 0 1
transp 0 0
clocks 0 1
clkpol 0 2
endbram
match $__XILINX_RAM64X1D
or_next_if_better
endmatch
match $__XILINX_RAM128X1D
endmatch endmatch

19
techlibs/xilinx/drams_bb.v
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@ -1,11 +1,20 @@
module RAM32X1D ( module RAM64X1D (
output DPO, SPO, output DPO, SPO,
input A0, A1, A2, A3, A4, D, input D, WCLK, WE,
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, input A0, A1, A2, A3, A4, A5,
input WCLK, WE input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
); );
parameter INIT = 32'h0; parameter INIT = 64'h0;
parameter IS_WCLK_INVERTED = 1'b0;
endmodule
module RAM128X1D (
output DPO, SPO,
input D, WCLK, WE,
input [6:0] A, DPRA
);
parameter INIT = 128'h0;
parameter IS_WCLK_INVERTED = 1'b0; parameter IS_WCLK_INVERTED = 1'b0;
endmodule endmodule

38
techlibs/xilinx/drams_map.v
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@ -1,17 +1,17 @@
module \$__XILINX_RAM32X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); module \$__XILINX_RAM64X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
parameter [31:0] INIT = 32'bx; parameter [63:0] INIT = 64'bx;
parameter CLKPOL2 = 1; parameter CLKPOL2 = 1;
input CLK1; input CLK1;
input [4:0] A1ADDR; input [5:0] A1ADDR;
output A1DATA; output A1DATA;
input [4:0] B1ADDR; input [5:0] B1ADDR;
input B1DATA; input B1DATA;
input B1EN; input B1EN;
RAM32X1D #( RAM64X1D #(
.INIT(INIT), .INIT(INIT),
.IS_WCLK_INVERTED(!CLKPOL2) .IS_WCLK_INVERTED(!CLKPOL2)
) _TECHMAP_REPLACE_ ( ) _TECHMAP_REPLACE_ (
@ -20,6 +20,7 @@ module \$__XILINX_RAM32X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
.DPRA2(A1ADDR[2]), .DPRA2(A1ADDR[2]),
.DPRA3(A1ADDR[3]), .DPRA3(A1ADDR[3]),
.DPRA4(A1ADDR[4]), .DPRA4(A1ADDR[4]),
.DPRA5(A1ADDR[5]),
.DPO(A1DATA), .DPO(A1DATA),
.A0(B1ADDR[0]), .A0(B1ADDR[0]),
@ -27,6 +28,33 @@ module \$__XILINX_RAM32X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
.A2(B1ADDR[2]), .A2(B1ADDR[2]),
.A3(B1ADDR[3]), .A3(B1ADDR[3]),
.A4(B1ADDR[4]), .A4(B1ADDR[4]),
.A5(B1ADDR[5]),
.D(B1DATA),
.WCLK(CLK1),
.WE(B1EN)
);
endmodule
module \$__XILINX_RAM128X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
parameter [127:0] INIT = 128'bx;
parameter CLKPOL2 = 1;
input CLK1;
input [6:0] A1ADDR;
output A1DATA;
input [6:0] B1ADDR;
input B1DATA;
input B1EN;
RAM128X1D #(
.INIT(INIT),
.IS_WCLK_INVERTED(!CLKPOL2)
) _TECHMAP_REPLACE_ (
.DPRA(A1ADDR),
.DPO(A1DATA),
.A(B1ADDR),
.D(B1DATA), .D(B1DATA),
.WCLK(CLK1), .WCLK(CLK1),
.WE(B1EN) .WE(B1EN)