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Fix stitching

This commit is contained in:
Eddie Hung 2019-02-13 17:04:23 -08:00
parent 13bf036bd6
commit 206f11dca3
1 changed files with 4 additions and 4 deletions
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8
passes/techmap/abc9.cc
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@ -653,6 +653,9 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
design->select(module, cell); design->select(module, cell);
} }
// FIXME: Better way to clean out module contents?
module->connections_.clear();
for (auto conn : mapped_mod->connections()) { for (auto conn : mapped_mod->connections()) {
if (!conn.first.is_fully_const()) { if (!conn.first.is_fully_const()) {
auto chunks = conn.first.chunks(); auto chunks = conn.first.chunks();
@ -660,7 +663,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
c.wire = module->wires_[remap_name(c.wire->name)]; c.wire = module->wires_[remap_name(c.wire->name)];
conn.first = std::move(chunks); conn.first = std::move(chunks);
} }
if (!conn.second.is_fully_const() && conn.second.is_wire()) { if (!conn.second.is_fully_const()) {
auto chunks = conn.second.chunks(); auto chunks = conn.second.chunks();
for (auto &c : chunks) for (auto &c : chunks)
c.wire = module->wires_[remap_name(c.wire->name)]; c.wire = module->wires_[remap_name(c.wire->name)];
@ -698,9 +701,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
// module->connect(conn); // module->connect(conn);
// } // }
// FIXME:
module->connections_.clear();
for (auto &it : mapped_mod->wires_) { for (auto &it : mapped_mod->wires_) {
RTLIL::Wire *w = it.second; RTLIL::Wire *w = it.second;
if (!w->port_input && !w->port_output) if (!w->port_input && !w->port_output)