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Code Issues Projects Releases Wiki Activity

Added "techmap -share_map" option

This commit is contained in:
Clifford Wolf 2013-11-24 19:50:25 +01:00
parent 019b301541
commit 20175afd29
2 changed files with 13 additions and 4 deletions
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9
passes/techmap/techmap.cc
View File

@ -372,6 +372,11 @@ struct TechmapPass : public Pass {
log(" transforms the internal RTL cells to the internal gate\n"); log(" transforms the internal RTL cells to the internal gate\n");
log(" library.\n"); log(" library.\n");
log("\n"); log("\n");
log(" -share_map filename\n");
log(" like -map, but look for the file in the share directory (where the\n");
log(" yosys data files are). this is mainly used internally when techmap\n");
log(" is called from other commands.\n");
log("\n");
log("When a module in the map file has the 'techmap_celltype' attribute set, it will\n"); log("When a module in the map file has the 'techmap_celltype' attribute set, it will\n");
log("match cells with a type that match the text value of this attribute.\n"); log("match cells with a type that match the text value of this attribute.\n");
log("\n"); log("\n");
@ -423,6 +428,10 @@ struct TechmapPass : public Pass {
map_files.push_back(args[++argidx]); map_files.push_back(args[++argidx]);
continue; continue;
} }
if (args[argidx] == "-share_map" && argidx+1 < args.size()) {
map_files.push_back(get_share_file_name(args[++argidx]));
continue;
}
break; break;
} }
extra_args(args, argidx, design); extra_args(args, argidx, design);

8
techlibs/xilinx/synth_xilinx.cc
View File

@ -82,7 +82,7 @@ struct SynthXilinxPass : public Pass {
log(" clean\n"); log(" clean\n");
log("\n"); log("\n");
log(" map_cells:\n"); log(" map_cells:\n");
log(" techmap -map <share_dir>/xilinx/cells.v\n"); log(" techmap -share_map xilinx/cells.v\n");
log(" clean\n"); log(" clean\n");
log("\n"); log("\n");
log(" clkbuf:\n"); log(" clkbuf:\n");
@ -94,7 +94,7 @@ struct SynthXilinxPass : public Pass {
log(" iopadmap -outpad OBUF I:O -inpad IBUF O:I @xilinx_nonclocks\n"); log(" iopadmap -outpad OBUF I:O -inpad IBUF O:I @xilinx_nonclocks\n");
log("\n"); log("\n");
log(" edif:\n"); log(" edif:\n");
log(" write_edif -top <top> synth.edif\n"); log(" write_edif synth.edif\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
@ -182,7 +182,7 @@ struct SynthXilinxPass : public Pass {
if (check_label(active, run_from, run_to, "map_cells")) if (check_label(active, run_from, run_to, "map_cells"))
{ {
Pass::call(design, stringf("techmap -map %s", get_share_file_name("xilinx/cells.v").c_str())); Pass::call(design, "techmap -share_map xilinx/cells.v");
Pass::call(design, "clean"); Pass::call(design, "clean");
} }
@ -201,7 +201,7 @@ struct SynthXilinxPass : public Pass {
if (check_label(active, run_from, run_to, "edif")) if (check_label(active, run_from, run_to, "edif"))
{ {
if (!edif_file.empty()) if (!edif_file.empty())
Pass::call(design, stringf("write_edif -top %s %s", top_module.c_str(), edif_file.c_str())); Pass::call(design, stringf("write_edif %s", edif_file.c_str()));
} }
log_pop(); log_pop();