riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Added tests for Verilog frontent for attributes on parameters and localparams 

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
This commit is contained in:
Maciej Kurc 2019-05-16 12:53:43 +02:00
parent ce4a0954bc
commit 1f52332b8d
2 changed files with 22 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
tests/simple/localparam_attr.v Normal file
View File

@ -0,0 +1,11 @@
module uut_localparam_attr (I, O);
(* LOCALPARAM_ATTRIBUTE = "attribute_content" *)
localparam WIDTH = 1;
input wire [WIDTH-1:0] I;
output wire [WIDTH-1:0] O;
assign O = I;
endmodule

11
tests/simple/param_attr.v Normal file
View File

@ -0,0 +1,11 @@
module uut_param_attr (I, O);
(* PARAMETER_ATTRIBUTE = "attribute_content" *)
parameter WIDTH = 1;
input wire [WIDTH-1:0] I;
output wire [WIDTH-1:0] O;
assign O = I;
endmodule