mirror of https://github.com/YosysHQ/yosys.git
Add extmodule support to firrtl backend
The current firrtl backend emits blackboxes as standard modules with an empty body, but this causes the firrtl compiler to optimize out entire circuits due to the absence of any drivers. Yosys already tags blackboxes with a (*blackbox*) attribute, so this commit just propagates this change to firrtl's syntax for blackboxes.
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@ -392,7 +392,37 @@ struct FirrtlWorker
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return result;
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}
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void run()
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void emit_extmodule()
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{
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std::string moduleFileinfo = getFileinfo(module);
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f << stringf(" extmodule %s: %s\n", make_id(module->name), moduleFileinfo.c_str());
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vector<string> port_decls;
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for (auto wire : module->wires())
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{
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const auto wireName = make_id(wire->name);
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std::string wireFileinfo = getFileinfo(wire);
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// Maybe not needed?
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if (wire->port_id)
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{
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if (wire->port_input && wire->port_output)
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{
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log_error("Module port %s.%s is inout!\n", log_id(module), log_id(wire));
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}
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port_decls.push_back(stringf(" %s %s: UInt<%d> %s\n", wire->port_input ? "input" : "output",
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wireName, wire->width, wireFileinfo.c_str()));
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}
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}
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for (auto str : port_decls) {
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f << str;
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}
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f << stringf("\n");
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}
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void emit_module()
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{
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std::string moduleFileinfo = getFileinfo(module);
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f << stringf(" module %s: %s\n", make_id(module->name), moduleFileinfo.c_str());
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@ -1076,6 +1106,22 @@ struct FirrtlWorker
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for (auto str : wire_exprs)
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f << str;
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f << stringf("\n");
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}
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void run()
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{
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// Blackboxes should be emitted as `extmodule`s in firrtl. Only ports are
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// emitted in such a case.
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if (module->get_blackbox_attribute())
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{
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emit_extmodule();
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}
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else
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{
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emit_module();
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}
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}
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};
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