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Added test_verific mode to tests/fsm/generate.py

This commit is contained in:
Clifford Wolf 2014-08-12 15:43:30 +02:00
parent e5ac8fdf2b
commit 1dd8252169
1 changed files with 17 additions and 7 deletions
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10
tests/fsm/generate.py
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@ -7,6 +7,9 @@ import sys
import random
from contextlib import contextmanager
# set to 'True' to compare verific with yosys
test_verific = False
@contextmanager
def redirect_stdout(new_target):
old_target, sys.stdout = sys.stdout, new_target
@ -86,6 +89,13 @@ for idx in range(50):
print(' end')
print('endmodule')
with file('temp/uut_%05d.ys' % idx, 'w') as f, redirect_stdout(f):
if test_verific:
print('read_verilog temp/uut_%05d.v' % idx)
print('proc;; rename uut_%05d gold' % idx)
print('verific -vlog2k temp/uut_%05d.v' % idx)
print('verific -import uut_%05d' % idx)
print('rename uut_%05d gate' % idx)
else:
print('read_verilog temp/uut_%05d.v' % idx)
print('proc;;')
print('copy uut_%05d gold' % idx)