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No need to punch ports at all

This commit is contained in:
Eddie Hung 2019-09-30 17:02:20 -07:00
parent 390b960c8c
commit 1b96d29174
2 changed files with 24 additions and 13 deletions
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24
backends/aiger/xaiger.cc
View File

@ -481,6 +481,7 @@ struct XAigerWriter
} }
} }
// Connect $currQ as an input to the flop box
if (box_module->get_bool_attribute("\\abc9_flop")) { if (box_module->get_bool_attribute("\\abc9_flop")) {
IdString port_name = "\\$currQ"; IdString port_name = "\\$currQ";
Wire *w = box_module->wire(port_name); Wire *w = box_module->wire(port_name);
@ -786,6 +787,29 @@ struct XAigerWriter
} }
} }
// For flops only, create an extra input for $currQ
if (box_module->get_bool_attribute("\\abc9_flop")) {
log_assert(holes_cell);
Wire *w = box_module->wire("\\$currQ");
Wire *holes_wire;
RTLIL::SigSpec port_wire;
for (int i = 0; i < GetSize(w); i++) {
box_inputs++;
holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
if (!holes_wire) {
holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
holes_wire->port_input = true;
holes_wire->port_id = port_id++;
holes_module->ports.push_back(holes_wire->name);
}
port_wire.append(holes_wire);
}
w = holes_module->addWire(stringf("%s.$currQ", cell->name.c_str()), GetSize(w));
w->set_bool_attribute("\\hierconn");
holes_module->connect(w, port_wire);
}
write_h_buffer(box_inputs); write_h_buffer(box_inputs);
write_h_buffer(box_outputs); write_h_buffer(box_outputs);
write_h_buffer(box_module->attributes.at("\\abc_box_id").as_int()); write_h_buffer(box_module->attributes.at("\\abc_box_id").as_int());

13
passes/techmap/abc9.cc
View File

@ -1121,19 +1121,6 @@ struct Abc9Pass : public Pass {
Pass::call_on_module(design, derived_module, "proc"); Pass::call_on_module(design, derived_module, "proc");
SigMap derived_sigmap(derived_module); SigMap derived_sigmap(derived_module);
Wire *currQ = derived_module->wire("\\$currQ");
if (currQ == NULL)
log_error("'\\$currQ' is not a wire present in module '%s'.\n", log_id(cell->type));
log_assert(!currQ->port_output);
if (!currQ->port_input) {
currQ->port_input = true;
derived_module->ports.push_back(currQ->name);
currQ->port_id = GetSize(derived_module->ports);
#ifndef NDEBUG
derived_module->check();
#endif
}
SigSpec pattern; SigSpec pattern;
SigSpec with; SigSpec with;
for (auto &conn : cell->connections()) { for (auto &conn : cell->connections()) {