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Refactor ce{mux,pol} -> hold{mux,pol}

This commit is contained in:
Eddie Hung 2019-09-19 14:27:25 -07:00
parent 429c9852ce
commit 1a0f7ed09c
2 changed files with 77 additions and 77 deletions
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26
passes/pmgen/ice40_dsp.cc
View File

@ -31,15 +31,15 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
#if 1 #if 1
log("\n"); log("\n");
log("ffA: %s %s %s\n", log_id(st.ffA, "--"), log_id(st.ffAcemux, "--"), log_id(st.ffArstmux, "--")); log("ffA: %s %s %s\n", log_id(st.ffA, "--"), log_id(st.ffAholdmux, "--"), log_id(st.ffArstmux, "--"));
log("ffB: %s %s %s\n", log_id(st.ffB, "--"), log_id(st.ffBcemux, "--"), log_id(st.ffBrstmux, "--")); log("ffB: %s %s %s\n", log_id(st.ffB, "--"), log_id(st.ffBholdmux, "--"), log_id(st.ffBrstmux, "--"));
log("ffCD: %s %s\n", log_id(st.ffCD, "--"), log_id(st.ffCDcemux, "--")); log("ffCD: %s %s\n", log_id(st.ffCD, "--"), log_id(st.ffCDholdmux, "--"));
log("mul: %s\n", log_id(st.mul, "--")); log("mul: %s\n", log_id(st.mul, "--"));
log("ffFJKG: %s\n", log_id(st.ffFJKG, "--")); log("ffFJKG: %s\n", log_id(st.ffFJKG, "--"));
log("ffH: %s\n", log_id(st.ffH, "--")); log("ffH: %s\n", log_id(st.ffH, "--"));
log("add: %s\n", log_id(st.add, "--")); log("add: %s\n", log_id(st.add, "--"));
log("mux: %s\n", log_id(st.mux, "--")); log("mux: %s\n", log_id(st.mux, "--"));
log("ffO: %s %s %s\n", log_id(st.ffO, "--"), log_id(st.ffOcemux, "--"), log_id(st.ffOrstmux, "--")); log("ffO: %s %s %s\n", log_id(st.ffO, "--"), log_id(st.ffOholdmux, "--"), log_id(st.ffOrstmux, "--"));
#endif #endif
log("Checking %s.%s for iCE40 DSP inference.\n", log_id(pm.module), log_id(st.mul)); log("Checking %s.%s for iCE40 DSP inference.\n", log_id(pm.module), log_id(st.mul));
@ -99,16 +99,16 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
cell->setParam("\\D_REG", st.ffCD ? State::S1 : State::S0); cell->setParam("\\D_REG", st.ffCD ? State::S1 : State::S0);
SigSpec AHOLD, BHOLD, CDHOLD; SigSpec AHOLD, BHOLD, CDHOLD;
if (st.ffAcemux) if (st.ffAholdmux)
AHOLD = st.ffAcepol ? pm.module->Not(NEW_ID, st.ffAcemux->getPort("\\S")) : st.ffAcemux->getPort("\\S"); AHOLD = st.ffAholdpol ? st.ffAholdmux->getPort("\\S") : pm.module->Not(NEW_ID, st.ffAholdmux->getPort("\\S"));
else else
AHOLD = State::S0; AHOLD = State::S0;
if (st.ffBcemux) if (st.ffBholdmux)
BHOLD = st.ffBcepol ? pm.module->Not(NEW_ID, st.ffBcemux->getPort("\\S")) : st.ffBcemux->getPort("\\S"); BHOLD = st.ffBholdpol ? st.ffBholdmux->getPort("\\S") : pm.module->Not(NEW_ID, st.ffBholdmux->getPort("\\S"));
else else
BHOLD = State::S0; BHOLD = State::S0;
if (st.ffCDcemux) if (st.ffCDholdmux)
CDHOLD = st.ffCDcepol ? pm.module->Not(NEW_ID, st.ffCDcemux->getPort("\\S")) : st.ffCDcemux->getPort("\\S"); CDHOLD = st.ffCDholdpol ? st.ffCDholdmux->getPort("\\S") : pm.module->Not(NEW_ID, st.ffCDholdmux->getPort("\\S"));
else else
CDHOLD = State::S0; CDHOLD = State::S0;
cell->setPort("\\AHOLD", AHOLD); cell->setPort("\\AHOLD", AHOLD);
@ -210,8 +210,8 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
} }
SigSpec OHOLD; SigSpec OHOLD;
if (st.ffOcemux) if (st.ffOholdmux)
OHOLD = st.ffOcemux ? pm.module->Not(NEW_ID, st.ffOcemux->getPort("\\S")) : st.ffOcemux->getPort("\\S"); OHOLD = st.ffOholdpol ? st.ffOholdmux->getPort("\\S") : pm.module->Not(NEW_ID, st.ffOholdmux->getPort("\\S"));
else else
OHOLD = State::S0; OHOLD = State::S0;
cell->setPort("\\OHOLDTOP", OHOLD); cell->setPort("\\OHOLDTOP", OHOLD);
@ -219,7 +219,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
SigSpec ORST; SigSpec ORST;
if (st.ffOrstmux) if (st.ffOrstmux)
ORST = st.ffOrstmux ? st.ffOrstmux->getPort("\\S") : pm.module->Not(NEW_ID, st.ffOrstmux->getPort("\\S")); ORST = st.ffOrstpol ? st.ffOrstmux->getPort("\\S") : pm.module->Not(NEW_ID, st.ffOrstmux->getPort("\\S"));
else else
ORST = State::S0; ORST = State::S0;
cell->setPort("\\ORSTTOP", ORST); cell->setPort("\\ORSTTOP", ORST);

128
passes/pmgen/ice40_dsp.pmg
View File

@ -6,20 +6,20 @@ state <SigSpec> sigA sigB sigCD sigH sigO
state <Cell*> add mux state <Cell*> add mux
state <IdString> addAB muxAB state <IdString> addAB muxAB
state <bool> ffAcepol ffBcepol ffCDcepol ffOcepol state <bool> ffAholdpol ffBholdpol ffCDholdpol ffOholdpol
state <bool> ffArstpol ffBrstpol ffCDrstpol ffOrstpol state <bool> ffArstpol ffBrstpol ffCDrstpol ffOrstpol
state <Cell*> ffA ffAcemux ffArstmux ffB ffBcemux ffBrstmux ffCD ffCDcemux state <Cell*> ffA ffAholdmux ffArstmux ffB ffBholdmux ffBrstmux ffCD ffCDholdmux
state <Cell*> ffFJKG ffH ffO ffOcemux ffOrstmux state <Cell*> ffFJKG ffH ffO ffOholdmux ffOrstmux
// subpattern // subpattern
state <SigSpec> argQ argD state <SigSpec> argQ argD
state <bool> ffcepol ffrstpol state <bool> ffholdpol ffrstpol
state <int> ffoffset state <int> ffoffset
udata <SigSpec> dffD dffQ udata <SigSpec> dffD dffQ
udata <SigBit> dffclock udata <SigBit> dffclock
udata <Cell*> dff dffcemux dffrstmux udata <Cell*> dff dffholdmux dffrstmux
udata <bool> dffcepol dffrstpol dffclock_pol udata <bool> dffholdpol dffrstpol dffclock_pol
match mul match mul
select mul->type.in($mul, \SB_MAC16) select mul->type.in($mul, \SB_MAC16)
@ -63,7 +63,7 @@ code sigA sigB sigH
log_assert(nusers(O.extract_end(i)) <= 1); log_assert(nusers(O.extract_end(i)) <= 1);
endcode endcode
code argQ ffA ffAcemux ffArstmux ffAcepol ffArstpol sigA clock clock_pol code argQ ffA ffAholdmux ffArstmux ffAholdpol ffArstpol sigA clock clock_pol
if (mul->type != \SB_MAC16 || !param(mul, \A_REG).as_bool()) { if (mul->type != \SB_MAC16 || !param(mul, \A_REG).as_bool()) {
argQ = sigA; argQ = sigA;
subpattern(in_dffe); subpattern(in_dffe);
@ -75,16 +75,16 @@ code argQ ffA ffAcemux ffArstmux ffAcepol ffArstpol sigA clock clock_pol
ffArstmux = dffrstmux; ffArstmux = dffrstmux;
ffArstpol = dffrstpol; ffArstpol = dffrstpol;
} }
if (dffcemux) { if (dffholdmux) {
ffAcemux = dffcemux; ffAholdmux = dffholdmux;
ffAcepol = dffcepol; ffAholdpol = dffholdpol;
} }
sigA = dffD; sigA = dffD;
} }
} }
endcode endcode
code argQ ffB ffBcemux ffBrstmux ffBcepol ffBrstpol sigB clock clock_pol code argQ ffB ffBholdmux ffBrstmux ffBholdpol ffBrstpol sigB clock clock_pol
if (mul->type != \SB_MAC16 || !param(mul, \B_REG).as_bool()) { if (mul->type != \SB_MAC16 || !param(mul, \B_REG).as_bool()) {
argQ = sigB; argQ = sigB;
subpattern(in_dffe); subpattern(in_dffe);
@ -96,9 +96,9 @@ code argQ ffB ffBcemux ffBrstmux ffBcepol ffBrstpol sigB clock clock_pol
ffBrstmux = dffrstmux; ffBrstmux = dffrstmux;
ffBrstpol = dffrstpol; ffBrstpol = dffrstpol;
} }
if (dffcemux) { if (dffholdmux) {
ffBcemux = dffcemux; ffBholdmux = dffholdmux;
ffBcepol = dffcepol; ffBholdpol = dffholdpol;
} }
sigB = dffD; sigB = dffD;
} }
@ -113,7 +113,7 @@ code argD ffFJKG sigH sigO clock clock_pol
subpattern(out_dffe); subpattern(out_dffe);
if (dff) { if (dff) {
// F/J/K/G do not have a CE-like (hold) input // F/J/K/G do not have a CE-like (hold) input
if (dffcemux) if (dffholdmux)
goto reject_ffFJKG; goto reject_ffFJKG;
// Reset signal of F/J (IRSTTOP) and K/G (IRSTBOT) // Reset signal of F/J (IRSTTOP) and K/G (IRSTBOT)
@ -154,7 +154,7 @@ code argD ffH sigH sigO clock clock_pol
subpattern(out_dffe); subpattern(out_dffe);
if (dff) { if (dff) {
// H does not have a CE-like (hold) input // H does not have a CE-like (hold) input
if (dffcemux) if (dffholdmux)
goto reject_ffH; goto reject_ffH;
// Reset signal of H (IRSTBOT) shared with B // Reset signal of H (IRSTBOT) shared with B
@ -226,7 +226,7 @@ code sigO
sigO = port(mux, \Y); sigO = port(mux, \Y);
endcode endcode
code argD ffO ffOcemux ffOrstmux ffOcepol ffOrstpol sigO sigCD clock clock_pol cd_signed o_lo code argD ffO ffOholdmux ffOrstmux ffOholdpol ffOrstpol sigO sigCD clock clock_pol cd_signed o_lo
if (mul->type != \SB_MAC16 || if (mul->type != \SB_MAC16 ||
// Ensure that register is not already used // Ensure that register is not already used
((mul->parameters.at(\TOPOUTPUT_SELECT, 0).as_int() != 1 && mul->parameters.at(\BOTOUTPUT_SELECT, 0).as_int() != 1) && ((mul->parameters.at(\TOPOUTPUT_SELECT, 0).as_int() != 1 && mul->parameters.at(\BOTOUTPUT_SELECT, 0).as_int() != 1) &&
@ -258,9 +258,9 @@ code argD ffO ffOcemux ffOrstmux ffOcepol ffOrstpol sigO sigCD clock clock_pol c
ffOrstmux = dffrstmux; ffOrstmux = dffrstmux;
ffOrstpol = dffrstpol; ffOrstpol = dffrstpol;
} }
if (dffcemux) { if (dffholdmux) {
ffOcemux = dffcemux; ffOholdmux = dffholdmux;
ffOcepol = dffcepol; ffOholdpol = dffholdpol;
} }
sigO.replace(sigO.extract(0, GetSize(dffQ)), dffQ); sigO.replace(sigO.extract(0, GetSize(dffQ)), dffQ);
@ -278,15 +278,15 @@ code argD ffO ffOcemux ffOrstmux ffOcepol ffOrstpol sigO sigCD clock clock_pol c
} }
endcode endcode
code argQ ffCD ffCDcemux ffCDcepol ffCDrstpol sigCD clock clock_pol code argQ ffCD ffCDholdmux ffCDholdpol ffCDrstpol sigCD clock clock_pol
if (!sigCD.empty() && if (!sigCD.empty() &&
(mul->type != \SB_MAC16 || (!param(mul, \C_REG).as_bool() && !param(mul, \D_REG).as_bool()))) { (mul->type != \SB_MAC16 || (!param(mul, \C_REG).as_bool() && !param(mul, \D_REG).as_bool()))) {
argQ = sigCD; argQ = sigCD;
subpattern(in_dffe); subpattern(in_dffe);
if (dff) { if (dff) {
if (dffcemux) { if (dffholdmux) {
ffCDcemux = dffcemux; ffCDholdmux = dffholdmux;
ffCDcepol = dffcepol; ffCDholdpol = dffholdpol;
} }
// Reset signal of C (IRSTTOP) and D (IRSTBOT) // Reset signal of C (IRSTTOP) and D (IRSTBOT)
@ -403,7 +403,7 @@ code argD
argD = port(ffrstmux, ffrstpol ? \A : \B); argD = port(ffrstmux, ffrstpol ? \A : \B);
dffD.replace(port(ffrstmux, \Y), argD); dffD.replace(port(ffrstmux, \Y), argD);
// Only search for ffcemux if argQ has at // Only search for ffholdmux if argQ has at
// least 3 users (ff, <upstream>, ffrstmux) and // least 3 users (ff, <upstream>, ffrstmux) and
// dffD only has two (ff, ffrstmux) // dffD only has two (ff, ffrstmux)
if (!(nusers(argQ) >= 3 && nusers(dffD) == 2)) if (!(nusers(argQ) >= 3 && nusers(dffD) == 2))
@ -413,26 +413,26 @@ code argD
dffrstmux = nullptr; dffrstmux = nullptr;
endcode endcode
match ffcemux match ffholdmux
if !argD.empty() if !argD.empty()
select ffcemux->type.in($mux) select ffholdmux->type.in($mux)
index <SigSpec> port(ffcemux, \Y) === argD index <SigSpec> port(ffholdmux, \Y) === argD
choice <IdString> AB {\A, \B} choice <IdString> BA {\B, \A}
index <SigSpec> port(ffcemux, AB) === argQ index <SigSpec> port(ffholdmux, BA) === argQ
define <bool> pol (AB == \A) define <bool> pol (BA == \B)
set ffcepol pol set ffholdpol pol
semioptional semioptional
endmatch endmatch
code argD code argD
if (ffcemux) { if (ffholdmux) {
dffcemux = ffcemux; dffholdmux = ffholdmux;
dffcepol = ffcepol; dffholdpol = ffholdpol;
argD = port(ffcemux, ffcepol ? \B : \A); argD = port(ffholdmux, ffholdpol ? \A : \B);
dffD.replace(port(ffcemux, \Y), argD); dffD.replace(port(ffholdmux, \Y), argD);
} }
else else
dffcemux = nullptr; dffholdmux = nullptr;
endcode endcode
// ####################### // #######################
@ -447,41 +447,41 @@ code
reject; reject;
endcode endcode
match ffcemux match ffholdmux
select ffcemux->type.in($mux) select ffholdmux->type.in($mux)
// ffcemux output must have two users: ffcemux and ff.D // ffholdmux output must have two users: ffholdmux and ff.D
select nusers(port(ffcemux, \Y)) == 2 select nusers(port(ffholdmux, \Y)) == 2
choice <IdString> AB {\A, \B} choice <IdString> BA {\B, \A}
// keep-last-value net must have at least three users: ffcemux, ff, downstream sink(s) // keep-last-value net must have at least three users: ffholdmux, ff, downstream sink(s)
select nusers(port(ffcemux, AB)) >= 3 select nusers(port(ffholdmux, BA)) >= 3
slice offset GetSize(port(ffcemux, \Y)) slice offset GetSize(port(ffholdmux, \Y))
define <IdString> BA (AB == \A ? \B : \A) define <IdString> AB (BA == \B ? \A : \B)
index <SigBit> port(ffcemux, BA)[offset] === argD[0] index <SigBit> port(ffholdmux, AB)[offset] === argD[0]
// Check that the rest of argD is present // Check that the rest of argD is present
filter GetSize(port(ffcemux, BA)) >= offset + GetSize(argD) filter GetSize(port(ffholdmux, AB)) >= offset + GetSize(argD)
filter port(ffcemux, BA).extract(offset, GetSize(argD)) == argD filter port(ffholdmux, AB).extract(offset, GetSize(argD)) == argD
set ffoffset offset set ffoffset offset
define <bool> pol (BA == \B) define <bool> pol (BA == \B)
set ffcepol pol set ffholdpol pol
semioptional semioptional
endmatch endmatch
code argD argQ code argD argQ
dffcemux = ffcemux; dffholdmux = ffholdmux;
if (ffcemux) { if (ffholdmux) {
SigSpec BA = port(ffcemux, ffcepol ? \B : \A); SigSpec AB = port(ffholdmux, ffholdpol ? \A : \B);
SigSpec Y = port(ffcemux, \Y); SigSpec Y = port(ffholdmux, \Y);
argQ = argD; argQ = argD;
argD.replace(BA, Y); argD.replace(AB, Y);
argQ.replace(BA, port(ffcemux, ffcepol ? \A : \B)); argQ.replace(AB, port(ffholdmux, ffholdpol ? \B : \A));
dffcemux = ffcemux; dffholdmux = ffholdmux;
dffcepol = ffcepol; dffholdpol = ffholdpol;
} }
endcode endcode
@ -499,7 +499,7 @@ match ffrstmux
index <SigBit> port(ffrstmux, AB)[offset] === argD[0] index <SigBit> port(ffrstmux, AB)[offset] === argD[0]
// Check that offset is consistent // Check that offset is consistent
filter !ffcemux || ffoffset == offset filter !ffholdmux || ffoffset == offset
// Check that the rest of argD is present // Check that the rest of argD is present
filter GetSize(port(ffrstmux, AB)) >= offset + GetSize(argD) filter GetSize(port(ffrstmux, AB)) >= offset + GetSize(argD)
filter port(ffrstmux, AB).extract(offset, GetSize(argD)) == argD filter port(ffrstmux, AB).extract(offset, GetSize(argD)) == argD
@ -532,12 +532,12 @@ match ff
index <SigBit> port(ff, \D)[offset] === argD[0] index <SigBit> port(ff, \D)[offset] === argD[0]
// Check that offset is consistent // Check that offset is consistent
filter (!ffcemux && !ffrstmux) || ffoffset == offset filter (!ffholdmux && !ffrstmux) || ffoffset == offset
// Check that the rest of argD is present // Check that the rest of argD is present
filter GetSize(port(ff, \D)) >= offset + GetSize(argD) filter GetSize(port(ff, \D)) >= offset + GetSize(argD)
filter port(ff, \D).extract(offset, GetSize(argD)) == argD filter port(ff, \D).extract(offset, GetSize(argD)) == argD
// Check that FF.Q is connected to CE-mux // Check that FF.Q is connected to CE-mux
filter !ffcemux || port(ff, \Q).extract(offset, GetSize(argQ)) == argQ filter !ffholdmux || port(ff, \Q).extract(offset, GetSize(argQ)) == argQ
set ffoffset offset set ffoffset offset
endmatch endmatch
@ -552,7 +552,7 @@ code argQ
} }
SigSpec D = port(ff, \D); SigSpec D = port(ff, \D);
SigSpec Q = port(ff, \Q); SigSpec Q = port(ff, \Q);
if (!ffcemux) { if (!ffholdmux) {
argQ = argD; argQ = argD;
argQ.replace(D, Q); argQ.replace(D, Q);
} }
@ -569,6 +569,6 @@ code argQ
dffclock_pol = param(ff, \CLK_POLARITY).as_bool(); dffclock_pol = param(ff, \CLK_POLARITY).as_bool();
} }
// No enable/reset mux possible without flop // No enable/reset mux possible without flop
else if (dffcemux || dffrstmux) else if (dffholdmux || dffrstmux)
reject; reject;
endcode endcode