mirror of https://github.com/YosysHQ/yosys.git
Formatting fixes
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1f1b64b880
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1688a62500
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@ -396,26 +396,23 @@ struct FirrtlWorker
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{
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{
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std::string moduleFileinfo = getFileinfo(module);
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std::string moduleFileinfo = getFileinfo(module);
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f << stringf(" extmodule %s: %s\n", make_id(module->name), moduleFileinfo.c_str());
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f << stringf(" extmodule %s: %s\n", make_id(module->name), moduleFileinfo.c_str());
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vector<string> port_decls;
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vector<std::string> port_decls;
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for (auto wire : module->wires())
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for (auto wire : module->wires())
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{
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{
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const auto wireName = make_id(wire->name);
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const auto wireName = make_id(wire->name);
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std::string wireFileinfo = getFileinfo(wire);
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std::string wireFileinfo = getFileinfo(wire);
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// Maybe not needed?
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if (wire->port_input && wire->port_output)
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if (wire->port_id)
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{
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{
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if (wire->port_input && wire->port_output)
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log_error("Module port %s.%s is inout!\n", log_id(module), log_id(wire));
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{
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log_error("Module port %s.%s is inout!\n", log_id(module), log_id(wire));
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}
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port_decls.push_back(stringf(" %s %s: UInt<%d> %s\n", wire->port_input ? "input" : "output",
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wireName, wire->width, wireFileinfo.c_str()));
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}
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}
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port_decls.push_back(stringf(" %s %s: UInt<%d> %s\n", wire->port_input ? "input" : "output",
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wireName, wire->width, wireFileinfo.c_str()));
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}
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}
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for (auto str : port_decls) {
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for (auto &str : port_decls)
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{
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f << str;
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f << str;
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}
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}
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@ -1115,13 +1112,9 @@ struct FirrtlWorker
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// Blackboxes should be emitted as `extmodule`s in firrtl. Only ports are
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// Blackboxes should be emitted as `extmodule`s in firrtl. Only ports are
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// emitted in such a case.
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// emitted in such a case.
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if (module->get_blackbox_attribute())
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if (module->get_blackbox_attribute())
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{
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emit_extmodule();
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emit_extmodule();
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}
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else
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else
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{
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emit_module();
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emit_module();
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}
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}
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}
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};
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};
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