riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Missing an '&'

This commit is contained in:
Eddie Hung 2019-09-26 11:13:08 -07:00
parent a009314597
commit 143f82def2
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
techlibs/xilinx/synth_xilinx.cc
View File

@ -244,7 +244,7 @@ struct SynthXilinxPass : public ScriptPass
} }
extra_args(args, argidx, design); extra_args(args, argidx, design);
if (family != "xcup" && family != "xcu" && family != "xc7" && family != "xc6v" & family != "xc6s") if (family != "xcup" && family != "xcu" && family != "xc7" && family != "xc6v" && family != "xc6s")
log_cmd_error("Invalid Xilinx -family setting: '%s'.\n", family.c_str()); log_cmd_error("Invalid Xilinx -family setting: '%s'.\n", family.c_str());
if (widemux != 0 && widemux < 2) if (widemux != 0 && widemux < 2)