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xilinx: improve specify functionality

This commit is contained in:
Eddie Hung 2020-02-12 15:25:30 -08:00
parent 46a89d7264
commit 12d70ca8fb
8 changed files with 547 additions and 466 deletions
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7
README.md
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@ -364,8 +364,13 @@ Verilog Attributes and non-standard features
it as the external-facing pin of an I/O pad, and prevents ``iopadmap``
from inserting another pad cell on it.
- The module attribute ``abc9_lut`` is an integer attribute marking to `abc9`
that this module describes a LUT with propagation delays described using
`specify` statements.
- The module attribute ``abc9_box`` is a boolean specifying a blackbox or
whitebox definition for use by `abc9`.
whitebox definition, with propagation delays described using `specify`
statements, for use by `abc9`.
- The port attribute ``abc9_carry`` marks the carry-in (if an input port) and
carry-out (if output port) ports of a box. This information is necessary for

3
backends/aiger/xaiger.cc
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@ -227,6 +227,9 @@ struct XAigerWriter
continue;
}
if (cell->type.in("$specify2", "$specify3", "$specrule"))
continue;
if (inst_module) {
bool abc9_flop = false;
auto it = cell->attributes.find("\\abc9_box_seq");

38
passes/techmap/abc9_ops.cc
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@ -380,8 +380,10 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
void prep_delays(RTLIL::Design *design)
{
// Derive and collect all blackbox modules, and collect all blackbox instantiations
pool<Module*> derived;
// Derive and collect all Yosys blackbox modules that are not combinatorial abc9 boxes
// (e.g. DSPs, RAMs, etc.) nor abc9 flops and collect all such instantiations
pool<Module*> blackboxes;
pool<Module*> flops;
std::vector<Cell*> cells;
for (auto module : design->selected_modules()) {
if (module->processes.size() > 0) {
@ -400,42 +402,38 @@ void prep_delays(RTLIL::Design *design)
continue;
if (inst_module->attributes.count(ID(abc9_box)))
continue;
IdString derived_type = inst_module->derive(design, cell->parameters);
inst_module = design->module(derived_type);
IdString blackboxes_type = inst_module->derive(design, cell->parameters);
inst_module = design->module(blackboxes_type);
log_assert(inst_module);
derived.insert(inst_module);
blackboxes.insert(inst_module);
if (inst_module->get_bool_attribute(ID(abc9_flop))) {
flops.insert(inst_module);
continue; // do not add $__ABC9_DELAY boxes to flops
// as delays will be captured in the flop box
}
cells.emplace_back(cell);
}
}
// Transform all $specify3 and $specrule to abc9_{arrival,required} attributes
std::vector<Module*> flops;
dict<SigBit, int> arrivals, requireds;
pool<Wire*> ports;
std::stringstream ss;
for (auto module : derived) {
if (module->get_bool_attribute(ID(abc9_flop)))
flops.push_back(module);
for (auto module : blackboxes) {
arrivals.clear();
requireds.clear();
for (auto cell : module->cells()) {
if (cell->type == ID($specify3)) {
auto src = cell->getPort(ID(SRC));
auto dat = cell->getPort(ID(DAT));
auto dst = cell->getPort(ID(DST));
for (const auto &c : src.chunks())
if (!c.wire->port_input)
log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src));
for (const auto &c : dat.chunks())
if (!c.wire->port_input)
log_error("Module '%s' contains specify cell '%s' where DAT '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(dat));
for (const auto &c : dst.chunks())
if (!c.wire->port_output)
log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", log_id(module), log_id(cell), log_signal(dst));
if (!cell->getParam(ID(EDGE_EN)).as_bool())
continue;
int rise_max = cell->getParam(ID(T_RISE_MAX)).as_int();
int fall_max = cell->getParam(ID(T_FALL_MAX)).as_int();
int max = std::max(rise_max,fall_max);
@ -443,7 +441,7 @@ void prep_delays(RTLIL::Design *design)
log_warning("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell));
continue;
}
for (auto d : dst)
for (const auto &d : dst)
arrivals[d] = std::max(arrivals[d], max);
}
else if (cell->type == ID($specrule)) {
@ -472,8 +470,10 @@ void prep_delays(RTLIL::Design *design)
continue;
ports.clear();
for (const auto &i : arrivals)
for (const auto &i : arrivals) {
log_dump(i.first, i.first.wire->name);
ports.insert(i.first.wire);
}
for (auto wire : ports) {
log_assert(wire->port_output);
ss.str("");
@ -1239,7 +1239,7 @@ struct Abc9OpsPass : public Pass {
log("\n");
log(" -prep_box\n");
log(" pre-compute the box library by analysing all modules marked with\n");
log(" (* abc9_box *)\n");
log(" (* abc9_box *).\n");
log("\n");
log(" -write_box <dst>\n");
log(" write the pre-computed box library to <dst>.\n");

86
techlibs/xilinx/abc9_map.v
View File

@ -398,8 +398,8 @@ module RAM32X1D (
.A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4),
.DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4)
);
$__ABC9_LUT6 spo (.A($SPO), .S({1'b1, A4, A3, A2, A1, A0}), .Y(SPO));
$__ABC9_LUT6 dpo (.A($DPO), .S({1'b1, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}), .Y(DPO));
$__ABC9_RAM6 spo (.A($SPO), .S({1'b1, A4, A3, A2, A1, A0}), .Y(SPO));
$__ABC9_RAM6 dpo (.A($DPO), .S({1'b1, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}), .Y(DPO));
endmodule
module RAM64X1D (
@ -421,8 +421,8 @@ module RAM64X1D (
.A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4), .A5(A5),
.DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4), .DPRA5(DPRA5)
);
$__ABC9_LUT6 spo (.A($SPO), .S({A5, A4, A3, A2, A1, A0}), .Y(SPO));
$__ABC9_LUT6 dpo (.A($DPO), .S({DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}), .Y(DPO));
$__ABC9_RAM6 spo (.A($SPO), .S({A5, A4, A3, A2, A1, A0}), .Y(SPO));
$__ABC9_RAM6 dpo (.A($DPO), .S({DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}), .Y(DPO));
endmodule
module RAM128X1D (
@ -443,8 +443,8 @@ module RAM128X1D (
.A(A),
.DPRA(DPRA)
);
$__ABC9_LUT7 spo (.A($SPO), .S(A), .Y(SPO));
$__ABC9_LUT7 dpo (.A($DPO), .S(DPRA), .Y(DPO));
$__ABC9_RAM7 spo (.A($SPO), .S(A), .Y(SPO));
$__ABC9_RAM7 dpo (.A($DPO), .S(DPRA), .Y(DPO));
endmodule
module RAM32M (
@ -478,14 +478,14 @@ module RAM32M (
.ADDRA(ADDRA), .ADDRB(ADDRB), .ADDRC(ADDRC), .ADDRD(ADDRD),
.DIA(DIA), .DIB(DIB), .DIC(DIC), .DID(DID)
);
$__ABC9_LUT6 doa0 (.A($DOA[0]), .S({1'b1, ADDRA}), .Y(DOA[0]));
$__ABC9_LUT6 doa1 (.A($DOA[1]), .S({1'b1, ADDRA}), .Y(DOA[1]));
$__ABC9_LUT6 dob0 (.A($DOB[0]), .S({1'b1, ADDRB}), .Y(DOB[0]));
$__ABC9_LUT6 dob1 (.A($DOB[1]), .S({1'b1, ADDRB}), .Y(DOB[1]));
$__ABC9_LUT6 doc0 (.A($DOC[0]), .S({1'b1, ADDRC}), .Y(DOC[0]));
$__ABC9_LUT6 doc1 (.A($DOC[1]), .S({1'b1, ADDRC}), .Y(DOC[1]));
$__ABC9_LUT6 dod0 (.A($DOD[0]), .S({1'b1, ADDRD}), .Y(DOD[0]));
$__ABC9_LUT6 dod1 (.A($DOD[1]), .S({1'b1, ADDRD}), .Y(DOD[1]));
$__ABC9_RAM6 doa0 (.A($DOA[0]), .S({1'b1, ADDRA}), .Y(DOA[0]));
$__ABC9_RAM6 doa1 (.A($DOA[1]), .S({1'b1, ADDRA}), .Y(DOA[1]));
$__ABC9_RAM6 dob0 (.A($DOB[0]), .S({1'b1, ADDRB}), .Y(DOB[0]));
$__ABC9_RAM6 dob1 (.A($DOB[1]), .S({1'b1, ADDRB}), .Y(DOB[1]));
$__ABC9_RAM6 doc0 (.A($DOC[0]), .S({1'b1, ADDRC}), .Y(DOC[0]));
$__ABC9_RAM6 doc1 (.A($DOC[1]), .S({1'b1, ADDRC}), .Y(DOC[1]));
$__ABC9_RAM6 dod0 (.A($DOD[0]), .S({1'b1, ADDRD}), .Y(DOD[0]));
$__ABC9_RAM6 dod1 (.A($DOD[1]), .S({1'b1, ADDRD}), .Y(DOD[1]));
endmodule
module RAM64M (
@ -519,10 +519,25 @@ module RAM64M (
.ADDRA(ADDRA), .ADDRB(ADDRB), .ADDRC(ADDRC), .ADDRD(ADDRD),
.DIA(DIA), .DIB(DIB), .DIC(DIC), .DID(DID)
);
$__ABC9_LUT6 doa (.A($DOA), .S(ADDRA), .Y(DOA));
$__ABC9_LUT6 dob (.A($DOB), .S(ADDRB), .Y(DOB));
$__ABC9_LUT6 doc (.A($DOC), .S(ADDRC), .Y(DOC));
$__ABC9_LUT6 dod (.A($DOD), .S(ADDRD), .Y(DOD));
$__ABC9_RAM6 doa (.A($DOA), .S(ADDRA), .Y(DOA));
$__ABC9_RAM6 dob (.A($DOB), .S(ADDRB), .Y(DOB));
$__ABC9_RAM6 doc (.A($DOC), .S(ADDRC), .Y(DOC));
$__ABC9_RAM6 dod (.A($DOD), .S(ADDRD), .Y(DOD));
endmodule
module SRL16 (
output Q,
(* techmap_autopurge *) input A0, A1, A2, A3, CLK, D
);
parameter [15:0] INIT = 16'h0000;
wire $Q;
SRL16 #(
.INIT(INIT),
) _TECHMAP_REPLACE_ (
.Q($Q),
.A0(A0), .A1(A1), .A2(A2), .A3(A3), .CLK(CLK), .D(D)
);
$__ABC9_RAM6 q (.A($Q), .S({1'b1, A3, A2, A1, A0, 1'b1}), .Y(Q));
endmodule
module SRL16E (
@ -538,7 +553,38 @@ module SRL16E (
.Q($Q),
.A0(A0), .A1(A1), .A2(A2), .A3(A3), .CE(CE), .CLK(CLK), .D(D)
);
$__ABC9_LUT6 q (.A($Q), .S({1'b1, A3, A2, A1, A0, 1'b1}), .Y(Q));
$__ABC9_RAM6 q (.A($Q), .S({1'b1, A3, A2, A1, A0, 1'b1}), .Y(Q));
endmodule
module SRLC16 (
output Q, Q15,
(* techmap_autopurge *) input A0, A1, A2, A3, CLK, D
);
parameter [15:0] INIT = 16'h0000;
wire $Q;
SRLC16 #(
.INIT(INIT),
) _TECHMAP_REPLACE_ (
.Q($Q), .Q(Q15),
.A0(A0), .A1(A1), .A2(A2), .A3(A3), .CLK(CLK), .D(D)
);
$__ABC9_RAM6 q (.A($Q), .S({1'b1, A3, A2, A1, A0, 1'b1}), .Y(Q));
endmodule
module SRLC16E (
output Q, Q15,
(* techmap_autopurge *) input A0, A1, A2, A3, CE, CLK, D
);
parameter [15:0] INIT = 16'h0000;
parameter [0:0] IS_CLK_INVERTED = 1'b0;
wire $Q;
SRLC16E #(
.INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED)
) _TECHMAP_REPLACE_ (
.Q($Q), .Q(Q15),
.A0(A0), .A1(A1), .A2(A2), .A3(A3), .CE(CE), .CLK(CLK), .D(D)
);
$__ABC9_RAM6 q (.A($Q), .S({1'b1, A3, A2, A1, A0, 1'b1}), .Y(Q));
endmodule
module SRLC32E (
@ -556,7 +602,7 @@ module SRLC32E (
.Q($Q), .Q31(Q31),
.A(A), .CE(CE), .CLK(CLK), .D(D)
);
$__ABC9_LUT6 q (.A($Q), .S({1'b1, A}), .Y(Q));
$__ABC9_RAM6 q (.A($Q), .S({1'b1, A}), .Y(Q));
endmodule
module DSP48E1 (

6
techlibs/xilinx/abc9_model.v
View File

@ -55,6 +55,7 @@ module \$__ABC9_ASYNC0 (input A, S, output Y);
assign Y = S ? 1'b0 : A;
specify
(A => Y) = 0;
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270
(S => Y) = 764;
endspecify
endmodule
@ -65,6 +66,7 @@ module \$__ABC9_ASYNC1 (input A, S, output Y);
assign Y = S ? 1'b1 : A;
specify
(A => Y) = 0;
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270
(S => Y) = 764;
endspecify
endmodule
@ -76,7 +78,7 @@ endmodule
// To model the combinatorial path, such cells have to be split
// into comb and seq parts, with this box modelling only the former.
(* abc9_box *)
module \$__ABC9_LUT6 (input A, input [5:0] S, output Y);
module \$__ABC9_RAM6 (input A, input [5:0] S, output Y);
specify
(S[0] => Y) = 642;
(S[1] => Y) = 631;
@ -88,7 +90,7 @@ module \$__ABC9_LUT6 (input A, input [5:0] S, output Y);
endmodule
// Box to emulate comb/seq behaviour of RAM128
(* abc9_box *)
module \$__ABC9_LUT7 (input A, input [6:0] S, output Y);
module \$__ABC9_RAM7 (input A, input [6:0] S, output Y);
specify
(S[0] => Y) = 1028;
(S[1] => Y) = 1017;

4
techlibs/xilinx/abc9_unmap.v
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@ -29,10 +29,10 @@ module $__ABC9_FF_(input D, output Q);
assign Q = D;
endmodule
module $__ABC9_LUT6(input A, input [5:0] S, output Y);
module $__ABC9_RAM6(input A, input [5:0] S, output Y);
assign Y = A;
endmodule
module $__ABC9_LUT7(input A, input [6:0] S, output Y);
module $__ABC9_RAM7(input A, input [6:0] S, output Y);
assign Y = A;
endmodule

753
techlibs/xilinx/cells_sim.v
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File diff suppressed because it is too large Load Diff

4
techlibs/xilinx/synth_xilinx.cc
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@ -619,8 +619,8 @@ struct SynthXilinxPass : public ScriptPass
if (dff_mode)
techmap_args += " -D DFF_MODE";
run("techmap " + techmap_args);
run("read_verilog -icells -specify -lib +/xilinx/abc9_model.v");
std::string abc9_opts = " -box +/xilinx/abc9_xc7.box";
run("read_verilog -icells -lib -specify +/xilinx/abc9_model.v");
std::string abc9_opts;
auto k = stringf("synth_xilinx.abc9.%s.W", family.c_str());
if (active_design->scratchpad.count(k))
abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str());