riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Merge pull request #2188 from antmicro/missing-operators 

Add logic-assignments operators
This commit is contained in:
whitequark 2020-06-26 07:30:27 +00:00 committed by GitHub
parent d6bdc09422 39c39848a2
commit 12c016ebdc
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
3 changed files with 132 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
frontends/verilog/verilog_lexer.l
View File

@ -526,6 +526,12 @@ import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ {
".*" { return TOK_WILDCARD_CONNECT; }
"|=" { SV_KEYWORD(TOK_OR_ASSIGN); }
"&=" { SV_KEYWORD(TOK_AND_ASSIGN); }
"+=" { SV_KEYWORD(TOK_PLUS_ASSIGN); }
"-=" { SV_KEYWORD(TOK_SUB_ASSIGN); }
"^=" { SV_KEYWORD(TOK_XOR_ASSIGN); }
[-+]?[=*]> {
if (!specify_mode) REJECT;
yylval->string = new std::string(yytext);

43
frontends/verilog/verilog_parser.y
View File

@ -256,7 +256,7 @@ static void rewriteAsMemoryNode(AstNode *node, AstNode *rangeNode)
%token TOK_PACKAGE TOK_ENDPACKAGE TOK_PACKAGESEP
%token TOK_INTERFACE TOK_ENDINTERFACE TOK_MODPORT TOK_VAR TOK_WILDCARD_CONNECT
%token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_WAND TOK_WOR TOK_REG TOK_LOGIC
%token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_ALWAYS TOK_INITIAL
%token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_PLUS_ASSIGN TOK_ALWAYS TOK_INITIAL
%token TOK_ALWAYS_FF TOK_ALWAYS_COMB TOK_ALWAYS_LATCH
%token TOK_BEGIN TOK_END TOK_IF TOK_ELSE TOK_FOR TOK_WHILE TOK_REPEAT
%token TOK_DPI_FUNCTION TOK_POSEDGE TOK_NEGEDGE TOK_OR TOK_AUTOMATIC
@ -270,6 +270,7 @@ static void rewriteAsMemoryNode(AstNode *node, AstNode *rangeNode)
%token TOK_RAND TOK_CONST TOK_CHECKER TOK_ENDCHECKER TOK_EVENTUALLY
%token TOK_INCREMENT TOK_DECREMENT TOK_UNIQUE TOK_PRIORITY
%token TOK_STRUCT TOK_PACKED TOK_UNSIGNED TOK_INT TOK_BYTE TOK_SHORTINT TOK_UNION
%token TOK_OR_ASSIGN TOK_XOR_ASSIGN TOK_AND_ASSIGN TOK_SUB_ASSIGN
%type <ast> range range_or_multirange non_opt_range non_opt_multirange range_or_signed_int
%type <ast> wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list
@ -2334,6 +2335,46 @@ simple_behavioral_stmt:
ast_stack.back()->children.push_back(node);
SET_AST_NODE_LOC(node, @2, @5);
append_attr(node, $1);
} |
attr lvalue TOK_XOR_ASSIGN delay expr {
AstNode *xor_node = new AstNode(AST_BIT_XOR, $2->clone(), $5);
AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, xor_node);
SET_AST_NODE_LOC(xor_node, @2, @5);
SET_AST_NODE_LOC(node, @2, @5);
ast_stack.back()->children.push_back(node);
append_attr(node, $1);
} |
attr lvalue TOK_OR_ASSIGN delay expr {
AstNode *or_node = new AstNode(AST_BIT_OR, $2->clone(), $5);
SET_AST_NODE_LOC(or_node, @2, @5);
AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, or_node);
SET_AST_NODE_LOC(node, @2, @5);
ast_stack.back()->children.push_back(node);
append_attr(node, $1);
} |
attr lvalue TOK_PLUS_ASSIGN delay expr {
AstNode *add_node = new AstNode(AST_ADD, $2->clone(), $5);
AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, add_node);
SET_AST_NODE_LOC(node, @2, @5);
SET_AST_NODE_LOC(add_node, @2, @5);
ast_stack.back()->children.push_back(node);
append_attr(node, $1);
} |
attr lvalue TOK_SUB_ASSIGN delay expr {
AstNode *sub_node = new AstNode(AST_SUB, $2->clone(), $5);
AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, sub_node);
SET_AST_NODE_LOC(node, @2, @5);
SET_AST_NODE_LOC(sub_node, @2, @5);
ast_stack.back()->children.push_back(node);
append_attr(node, $1);
} |
attr lvalue TOK_AND_ASSIGN delay expr {
AstNode *and_node = new AstNode(AST_BIT_AND, $2->clone(), $5);
AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, and_node);
SET_AST_NODE_LOC(node, @2, @5);
SET_AST_NODE_LOC(and_node, @2, @5);
ast_stack.back()->children.push_back(node);
append_attr(node, $1);
};
// this production creates the obligatory if-else shift/reduce conflict

83
tests/opt/opt_expr_combined_assign.ys Normal file
View File

@ -0,0 +1,83 @@
read_verilog -sv <<EOT
module opt_expr_or_test(input [3:0] i, input [7:0] j, output [8:0] o);
wire[8:0] a = 8'b0;
initial begin
a |= i;
a |= j;
end
assign o = a;
endmodule
EOT
proc
equiv_opt -assert opt_expr -fine
design -load postopt
select -assert-count 1 t:$or r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i
design -reset
read_verilog -sv <<EOT
module opt_expr_add_test(input [3:0] i, input [7:0] j, output [8:0] o);
wire[8:0] a = 8'b0;
initial begin
a += i;
a += j;
end
assign o = a;
endmodule
EOT
proc
equiv_opt -assert opt_expr -fine
design -load postopt
select -assert-count 1 t:$add r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
design -reset
read_verilog -sv <<EOT
module opt_expr_xor_test(input [3:0] i, input [7:0] j, output [8:0] o);
wire[8:0] a = 8'b0;
initial begin
a ^= i;
a ^= j;
end
assign o = a;
endmodule
EOT
proc
equiv_opt -assert opt_expr -fine
design -load postopt
select -assert-count 1 t:$xor r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i
design -reset
read_verilog -sv <<EOT
module opt_expr_sub_test(input [3:0] i, input [7:0] j, output [8:0] o);
wire[8:0] a = 8'b0;
initial begin
a -= i;
a -= j;
end
assign o = a;
endmodule
EOT
proc
equiv_opt -assert opt_expr -fine
design -load postopt
select -assert-count 1 t:$sub r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
design -reset
read_verilog -sv <<EOT
module opt_expr_and_test(input [3:0] i, input [7:0] j, output [8:0] o);
wire[8:0] a = 8'b11111111;
initial begin
a &= i;
a &= j;
end
assign o = a;
endmodule
EOT
proc
equiv_opt -assert opt_expr -fine
design -load postopt
select -assert-count 1 t:$and r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i