From 416a66aee822c999a28f580cbcdb24cdf4e73a13 Mon Sep 17 00:00:00 2001 From: Kamil Rakoczy Date: Wed, 3 Jun 2020 13:51:57 +0200 Subject: [PATCH 1/8] Add or-assignment operator Signed-off-by: Kamil Rakoczy --- frontends/verilog/verilog_lexer.l | 2 ++ frontends/verilog/verilog_parser.y | 10 +++++++++- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index e6fa6361e..ea85bf52e 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -526,6 +526,8 @@ import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ { ".*" { return TOK_WILDCARD_CONNECT; } +"|=" { SV_KEYWORD(TOK_OR_ASSIGN); } + [-+]?[=*]> { if (!specify_mode) REJECT; yylval->string = new std::string(yytext); diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 15c231f3b..f7a73b00e 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -259,7 +259,7 @@ static void rewriteAsMemoryNode(AstNode *node, AstNode *rangeNode) %token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_ALWAYS TOK_INITIAL %token TOK_ALWAYS_FF TOK_ALWAYS_COMB TOK_ALWAYS_LATCH %token TOK_BEGIN TOK_END TOK_IF TOK_ELSE TOK_FOR TOK_WHILE TOK_REPEAT -%token TOK_DPI_FUNCTION TOK_POSEDGE TOK_NEGEDGE TOK_OR TOK_AUTOMATIC +%token TOK_DPI_FUNCTION TOK_POSEDGE TOK_NEGEDGE TOK_OR TOK_OR_ASSIGN TOK_AUTOMATIC %token TOK_CASE TOK_CASEX TOK_CASEZ TOK_ENDCASE TOK_DEFAULT %token TOK_FUNCTION TOK_ENDFUNCTION TOK_TASK TOK_ENDTASK TOK_SPECIFY %token TOK_IGNORED_SPECIFY TOK_ENDSPECIFY TOK_SPECPARAM TOK_SPECIFY_AND TOK_IGNORED_SPECIFY_AND @@ -2334,6 +2334,14 @@ simple_behavioral_stmt: ast_stack.back()->children.push_back(node); SET_AST_NODE_LOC(node, @2, @5); append_attr(node, $1); + } | + attr lvalue TOK_OR_ASSIGN delay expr { + AstNode *or_node = new AstNode(AST_BIT_OR, $2->clone(), $5); + SET_AST_NODE_LOC(or_node, @2, @5); + AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, or_node); + SET_AST_NODE_LOC(node, @2, @5); + ast_stack.back()->children.push_back(node); + append_attr(node, $1); }; // this production creates the obligatory if-else shift/reduce conflict From 22408f24c7d9c8a648e854fad01aff37a0f9fbd9 Mon Sep 17 00:00:00 2001 From: Kamil Rakoczy Date: Wed, 3 Jun 2020 16:44:02 +0200 Subject: [PATCH 2/8] Add plus-assignment operator Signed-off-by: Kamil Rakoczy --- frontends/verilog/verilog_lexer.l | 1 + frontends/verilog/verilog_parser.y | 10 +++++++++- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index ea85bf52e..c77da4274 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -527,6 +527,7 @@ import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ { ".*" { return TOK_WILDCARD_CONNECT; } "|=" { SV_KEYWORD(TOK_OR_ASSIGN); } +"+=" { SV_KEYWORD(TOK_PLUS_ASSIGN); } [-+]?[=*]> { if (!specify_mode) REJECT; diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index f7a73b00e..e8b74cf83 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -256,7 +256,7 @@ static void rewriteAsMemoryNode(AstNode *node, AstNode *rangeNode) %token TOK_PACKAGE TOK_ENDPACKAGE TOK_PACKAGESEP %token TOK_INTERFACE TOK_ENDINTERFACE TOK_MODPORT TOK_VAR TOK_WILDCARD_CONNECT %token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_WAND TOK_WOR TOK_REG TOK_LOGIC -%token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_ALWAYS TOK_INITIAL +%token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_PLUS_ASSIGN TOK_ALWAYS TOK_INITIAL %token TOK_ALWAYS_FF TOK_ALWAYS_COMB TOK_ALWAYS_LATCH %token TOK_BEGIN TOK_END TOK_IF TOK_ELSE TOK_FOR TOK_WHILE TOK_REPEAT %token TOK_DPI_FUNCTION TOK_POSEDGE TOK_NEGEDGE TOK_OR TOK_OR_ASSIGN TOK_AUTOMATIC @@ -2342,6 +2342,14 @@ simple_behavioral_stmt: SET_AST_NODE_LOC(node, @2, @5); ast_stack.back()->children.push_back(node); append_attr(node, $1); + } | + attr lvalue TOK_PLUS_ASSIGN delay expr { + AstNode *add_node = new AstNode(AST_ADD, $2->clone(), $5); + AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, add_node); + SET_AST_NODE_LOC(node, @2, @5); + SET_AST_NODE_LOC(add_node, @2, @5); + ast_stack.back()->children.push_back(node); + append_attr(node, $1); }; // this production creates the obligatory if-else shift/reduce conflict From a5ca4eeefb13c24042bae36ea8f640b5529efd93 Mon Sep 17 00:00:00 2001 From: Kamil Rakoczy Date: Wed, 24 Jun 2020 11:45:38 +0200 Subject: [PATCH 3/8] Add or-assignment and plus-assignment tests Signed-off-by: Kamil Rakoczy --- tests/opt/opt_expr_or_assignment.ys | 15 +++++++++++++++ tests/opt/opt_expr_plus_assignment.ys | 15 +++++++++++++++ 2 files changed, 30 insertions(+) create mode 100644 tests/opt/opt_expr_or_assignment.ys create mode 100644 tests/opt/opt_expr_plus_assignment.ys diff --git a/tests/opt/opt_expr_or_assignment.ys b/tests/opt/opt_expr_or_assignment.ys new file mode 100644 index 000000000..21e08550f --- /dev/null +++ b/tests/opt/opt_expr_or_assignment.ys @@ -0,0 +1,15 @@ +read_verilog -sv < Date: Tue, 23 Jun 2020 18:50:50 +0200 Subject: [PATCH 4/8] Support missing xor-assign operator Signed-off-by: Lukasz Dalek --- frontends/verilog/verilog_lexer.l | 1 + frontends/verilog/verilog_parser.y | 10 +++++++++- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index c77da4274..8c9f403a3 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -528,6 +528,7 @@ import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ { "|=" { SV_KEYWORD(TOK_OR_ASSIGN); } "+=" { SV_KEYWORD(TOK_PLUS_ASSIGN); } +"^=" { SV_KEYWORD(TOK_XOR_ASSIGN); } [-+]?[=*]> { if (!specify_mode) REJECT; diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index e8b74cf83..4c2a78809 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -259,7 +259,7 @@ static void rewriteAsMemoryNode(AstNode *node, AstNode *rangeNode) %token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_PLUS_ASSIGN TOK_ALWAYS TOK_INITIAL %token TOK_ALWAYS_FF TOK_ALWAYS_COMB TOK_ALWAYS_LATCH %token TOK_BEGIN TOK_END TOK_IF TOK_ELSE TOK_FOR TOK_WHILE TOK_REPEAT -%token TOK_DPI_FUNCTION TOK_POSEDGE TOK_NEGEDGE TOK_OR TOK_OR_ASSIGN TOK_AUTOMATIC +%token TOK_DPI_FUNCTION TOK_POSEDGE TOK_NEGEDGE TOK_OR TOK_OR_ASSIGN TOK_XOR_ASSIGN TOK_AUTOMATIC %token TOK_CASE TOK_CASEX TOK_CASEZ TOK_ENDCASE TOK_DEFAULT %token TOK_FUNCTION TOK_ENDFUNCTION TOK_TASK TOK_ENDTASK TOK_SPECIFY %token TOK_IGNORED_SPECIFY TOK_ENDSPECIFY TOK_SPECPARAM TOK_SPECIFY_AND TOK_IGNORED_SPECIFY_AND @@ -2335,6 +2335,14 @@ simple_behavioral_stmt: SET_AST_NODE_LOC(node, @2, @5); append_attr(node, $1); } | + attr lvalue TOK_XOR_ASSIGN delay expr { + AstNode *xor_node = new AstNode(AST_BIT_XOR, $2->clone(), $5); + AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, xor_node); + SET_AST_NODE_LOC(xor_node, @2, @5); + SET_AST_NODE_LOC(node, @2, @5); + ast_stack.back()->children.push_back(node); + append_attr(node, $1); + } | attr lvalue TOK_OR_ASSIGN delay expr { AstNode *or_node = new AstNode(AST_BIT_OR, $2->clone(), $5); SET_AST_NODE_LOC(or_node, @2, @5); From f6d06c9f7b01641a657a9f69ef8ce9cb263ff47b Mon Sep 17 00:00:00 2001 From: Kamil Rakoczy Date: Wed, 24 Jun 2020 14:38:03 +0200 Subject: [PATCH 5/8] Add xor-assignment test Signed-off-by: Kamil Rakoczy --- tests/opt/opt_expr_xor_assignment.ys | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 tests/opt/opt_expr_xor_assignment.ys diff --git a/tests/opt/opt_expr_xor_assignment.ys b/tests/opt/opt_expr_xor_assignment.ys new file mode 100644 index 000000000..924185e09 --- /dev/null +++ b/tests/opt/opt_expr_xor_assignment.ys @@ -0,0 +1,15 @@ +read_verilog -sv < Date: Thu, 25 Jun 2020 13:29:06 +0200 Subject: [PATCH 6/8] Support missing sub-assign and and-assign operators Signed-off-by: Kamil Rakoczy --- frontends/verilog/verilog_lexer.l | 2 ++ frontends/verilog/verilog_parser.y | 21 +++++++++++++++++++-- 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index 8c9f403a3..028106381 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -527,7 +527,9 @@ import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ { ".*" { return TOK_WILDCARD_CONNECT; } "|=" { SV_KEYWORD(TOK_OR_ASSIGN); } +"&=" { SV_KEYWORD(TOK_AND_ASSIGN); } "+=" { SV_KEYWORD(TOK_PLUS_ASSIGN); } +"-=" { SV_KEYWORD(TOK_SUB_ASSIGN); } "^=" { SV_KEYWORD(TOK_XOR_ASSIGN); } [-+]?[=*]> { diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 4c2a78809..18b470bca 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -259,7 +259,7 @@ static void rewriteAsMemoryNode(AstNode *node, AstNode *rangeNode) %token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_PLUS_ASSIGN TOK_ALWAYS TOK_INITIAL %token TOK_ALWAYS_FF TOK_ALWAYS_COMB TOK_ALWAYS_LATCH %token TOK_BEGIN TOK_END TOK_IF TOK_ELSE TOK_FOR TOK_WHILE TOK_REPEAT -%token TOK_DPI_FUNCTION TOK_POSEDGE TOK_NEGEDGE TOK_OR TOK_OR_ASSIGN TOK_XOR_ASSIGN TOK_AUTOMATIC +%token TOK_DPI_FUNCTION TOK_POSEDGE TOK_NEGEDGE TOK_OR TOK_AUTOMATIC %token TOK_CASE TOK_CASEX TOK_CASEZ TOK_ENDCASE TOK_DEFAULT %token TOK_FUNCTION TOK_ENDFUNCTION TOK_TASK TOK_ENDTASK TOK_SPECIFY %token TOK_IGNORED_SPECIFY TOK_ENDSPECIFY TOK_SPECPARAM TOK_SPECIFY_AND TOK_IGNORED_SPECIFY_AND @@ -269,7 +269,8 @@ static void rewriteAsMemoryNode(AstNode *node, AstNode *rangeNode) %token TOK_POS_INDEXED TOK_NEG_INDEXED TOK_PROPERTY TOK_ENUM TOK_TYPEDEF %token TOK_RAND TOK_CONST TOK_CHECKER TOK_ENDCHECKER TOK_EVENTUALLY %token TOK_INCREMENT TOK_DECREMENT TOK_UNIQUE TOK_PRIORITY -%token TOK_STRUCT TOK_PACKED TOK_UNSIGNED TOK_INT TOK_BYTE TOK_SHORTINT TOK_UNION +%token TOK_STRUCT TOK_PACKED TOK_UNSIGNED TOK_INT TOK_BYTE TOK_SHORTINT TOK_UNION +%token TOK_OR_ASSIGN TOK_XOR_ASSIGN TOK_AND_ASSIGN TOK_SUB_ASSIGN %type range range_or_multirange non_opt_range non_opt_multirange range_or_signed_int %type wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list @@ -2358,6 +2359,22 @@ simple_behavioral_stmt: SET_AST_NODE_LOC(add_node, @2, @5); ast_stack.back()->children.push_back(node); append_attr(node, $1); + } | + attr lvalue TOK_SUB_ASSIGN delay expr { + AstNode *sub_node = new AstNode(AST_SUB, $2->clone(), $5); + AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, sub_node); + SET_AST_NODE_LOC(node, @2, @5); + SET_AST_NODE_LOC(sub_node, @2, @5); + ast_stack.back()->children.push_back(node); + append_attr(node, $1); + } | + attr lvalue TOK_AND_ASSIGN delay expr { + AstNode *and_node = new AstNode(AST_BIT_AND, $2->clone(), $5); + AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, and_node); + SET_AST_NODE_LOC(node, @2, @5); + SET_AST_NODE_LOC(and_node, @2, @5); + ast_stack.back()->children.push_back(node); + append_attr(node, $1); }; // this production creates the obligatory if-else shift/reduce conflict From 470df03f3d6731f0b784ceb4e1b05c8583b230a8 Mon Sep 17 00:00:00 2001 From: Kamil Rakoczy Date: Thu, 25 Jun 2020 14:17:41 +0200 Subject: [PATCH 7/8] Move combined assign tests to single file Signed-off-by: Kamil Rakoczy --- tests/opt/opt_expr_combined_assign.ys | 49 +++++++++++++++++++++++++++ tests/opt/opt_expr_or_assignment.ys | 15 -------- tests/opt/opt_expr_plus_assignment.ys | 15 -------- tests/opt/opt_expr_xor_assignment.ys | 15 -------- 4 files changed, 49 insertions(+), 45 deletions(-) create mode 100644 tests/opt/opt_expr_combined_assign.ys delete mode 100644 tests/opt/opt_expr_or_assignment.ys delete mode 100644 tests/opt/opt_expr_plus_assignment.ys delete mode 100644 tests/opt/opt_expr_xor_assignment.ys diff --git a/tests/opt/opt_expr_combined_assign.ys b/tests/opt/opt_expr_combined_assign.ys new file mode 100644 index 000000000..56fbac9de --- /dev/null +++ b/tests/opt/opt_expr_combined_assign.ys @@ -0,0 +1,49 @@ +read_verilog -sv < Date: Thu, 25 Jun 2020 14:20:47 +0200 Subject: [PATCH 8/8] Add sub-assign and and-assign tests Signed-off-by: Kamil Rakoczy --- tests/opt/opt_expr_combined_assign.ys | 34 +++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/tests/opt/opt_expr_combined_assign.ys b/tests/opt/opt_expr_combined_assign.ys index 56fbac9de..b18923c7b 100644 --- a/tests/opt/opt_expr_combined_assign.ys +++ b/tests/opt/opt_expr_combined_assign.ys @@ -47,3 +47,37 @@ equiv_opt -assert opt_expr -fine design -load postopt select -assert-count 1 t:$xor r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i + +design -reset +read_verilog -sv <