write_verilog: emit `initial $display` correctly.

backends/verilog/verilog_backend.cc

@@ -1896,6 +1896,9 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 
 void dump_sync_print(std::ostream &f, std::string indent, const RTLIL::SigSpec &trg, const RTLIL::Const &polarity, std::vector<const RTLIL::Cell*> &cells)
 {
+	if (trg.size() == 0) {
+		f << stringf("%s" "initial begin\n", indent.c_str());
+	} else {
 		f << stringf("%s" "always @(", indent.c_str());
 		for (int i = 0; i < trg.size(); i++) {
 			if (i != 0)
@@ -1907,6 +1910,7 @@ void dump_sync_print(std::ostream &f, std::string indent, const RTLIL::SigSpec &
 			dump_sigspec(f, trg[i]);
 		}
 		f << ") begin\n";
+	}
 
 	std::sort(cells.begin(), cells.end(), [](const RTLIL::Cell *a, const RTLIL::Cell *b) {
 		return a->getParam(ID::PRIORITY).as_int() > b->getParam(ID::PRIORITY).as_int();

docs/source/CHAPTER_CellLib.rst

@@ -661,6 +661,8 @@ Ports:
 
 ``\TRG``
 	The signals that control when this ``$print`` cell is triggered.
+	If the width of this port is zero and ``\TRG_ENABLE`` is true, the cell is
+	triggered during initial evaluation (time zero) only.
 
 ``\EN``
 	Enable signal for the whole cell.

frontends/ast/genrtlil.cc

@@ -718,7 +718,7 @@ struct AST_INTERNAL::ProcessGenerator
 					}
 				}
 				cell->parameters[ID::TRG_WIDTH] = triggers.size();
-				cell->parameters[ID::TRG_ENABLE] = !triggers.empty();
+				cell->parameters[ID::TRG_ENABLE] = (always->type == AST_INITIAL) || !triggers.empty();
 				cell->parameters[ID::TRG_POLARITY] = polarity;
 				cell->parameters[ID::PRIORITY] = --last_print_priority;
 				cell->setPort(ID::TRG, triggers);