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write_verilog: emit `initial $display` correctly.

This commit is contained in:
Catherine 2024-01-11 11:47:55 +00:00 committed by Dag Lem
parent 0486f61a35
commit 1159e48721
3 changed files with 18 additions and 12 deletions
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24
backends/verilog/verilog_backend.cc
View File

@ -1896,17 +1896,21 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
void dump_sync_print(std::ostream &f, std::string indent, const RTLIL::SigSpec &trg, const RTLIL::Const &polarity, std::vector<const RTLIL::Cell*> &cells) void dump_sync_print(std::ostream &f, std::string indent, const RTLIL::SigSpec &trg, const RTLIL::Const &polarity, std::vector<const RTLIL::Cell*> &cells)
{ {
f << stringf("%s" "always @(", indent.c_str()); if (trg.size() == 0) {
for (int i = 0; i < trg.size(); i++) { f << stringf("%s" "initial begin\n", indent.c_str());
if (i != 0) } else {
f << " or "; f << stringf("%s" "always @(", indent.c_str());
if (polarity[i]) for (int i = 0; i < trg.size(); i++) {
f << "posedge "; if (i != 0)
else f << " or ";
f << "negedge "; if (polarity[i])
dump_sigspec(f, trg[i]); f << "posedge ";
else
f << "negedge ";
dump_sigspec(f, trg[i]);
}
f << ") begin\n";
} }
f << ") begin\n";
std::sort(cells.begin(), cells.end(), [](const RTLIL::Cell *a, const RTLIL::Cell *b) { std::sort(cells.begin(), cells.end(), [](const RTLIL::Cell *a, const RTLIL::Cell *b) {
return a->getParam(ID::PRIORITY).as_int() > b->getParam(ID::PRIORITY).as_int(); return a->getParam(ID::PRIORITY).as_int() > b->getParam(ID::PRIORITY).as_int();

4
docs/source/CHAPTER_CellLib.rst
View File

@ -120,7 +120,7 @@ All binary RTL cells have two input ports ``\A`` and ``\B`` and one output port
:verilog:`Y = A >>> B` $sshr :verilog:`Y = A - B` $sub :verilog:`Y = A >>> B` $sshr :verilog:`Y = A - B` $sub
:verilog:`Y = A && B` $logic_and :verilog:`Y = A * B` $mul :verilog:`Y = A && B` $logic_and :verilog:`Y = A * B` $mul
:verilog:`Y = A || B` $logic_or :verilog:`Y = A / B` $div :verilog:`Y = A || B` $logic_or :verilog:`Y = A / B` $div
:verilog:`Y = A === B` $eqx :verilog:`Y = A % B` $mod :verilog:`Y = A === B` $eqx :verilog:`Y = A % B` $mod
:verilog:`Y = A !== B` $nex ``N/A`` $divfloor :verilog:`Y = A !== B` $nex ``N/A`` $divfloor
:verilog:`Y = A ** B` $pow ``N/A`` $modfoor :verilog:`Y = A ** B` $pow ``N/A`` $modfoor
======================= ============= ======================= ========= ======================= ============= ======================= =========
@ -661,6 +661,8 @@ Ports:
``\TRG`` ``\TRG``
The signals that control when this ``$print`` cell is triggered. The signals that control when this ``$print`` cell is triggered.
If the width of this port is zero and ``\TRG_ENABLE`` is true, the cell is
triggered during initial evaluation (time zero) only.
``\EN`` ``\EN``
Enable signal for the whole cell. Enable signal for the whole cell.

2
frontends/ast/genrtlil.cc
View File

@ -718,7 +718,7 @@ struct AST_INTERNAL::ProcessGenerator
} }
} }
cell->parameters[ID::TRG_WIDTH] = triggers.size(); cell->parameters[ID::TRG_WIDTH] = triggers.size();
cell->parameters[ID::TRG_ENABLE] = !triggers.empty(); cell->parameters[ID::TRG_ENABLE] = (always->type == AST_INITIAL) || !triggers.empty();
cell->parameters[ID::TRG_POLARITY] = polarity; cell->parameters[ID::TRG_POLARITY] = polarity;
cell->parameters[ID::PRIORITY] = --last_print_priority; cell->parameters[ID::PRIORITY] = --last_print_priority;
cell->setPort(ID::TRG, triggers); cell->setPort(ID::TRG, triggers);