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Check that whiteboxes are synthesisable

This commit is contained in:
Eddie Hung 2019-06-14 13:08:38 -07:00
parent 2d85725604
commit 0fa6a441f1
1 changed files with 8 additions and 4 deletions
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12
backends/aiger/xaiger.cc
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@ -722,7 +722,7 @@ struct XAigerWriter
write_h_buffer(box_list.size()); write_h_buffer(box_list.size());
RTLIL::Module *holes_module = nullptr; RTLIL::Module *holes_module = nullptr;
holes_module = module->design->addModule("\\__holes__"); holes_module = module->design->addModule("$__holes__");
log_assert(holes_module); log_assert(holes_module);
int port_id = 1; int port_id = 1;
@ -822,17 +822,21 @@ struct XAigerWriter
Pass::call(holes_module->design, "flatten -wb"); Pass::call(holes_module->design, "flatten -wb");
// TODO: Should techmap all lib_whitebox-es once // TODO: Should techmap/AIG all lib_whitebox-es once
Pass::call(holes_module->design, "techmap"); Pass::call(holes_module->design, "techmap");
Pass::call(holes_module->design, "aigmap"); Pass::call(holes_module->design, "aigmap");
Pass::call(holes_module->design, "clean -purge"); for (auto cell : holes_module->cells())
if (!cell->type.in("$_NOT_", "$_AND_"))
log_error("Whitebox contents cannot be represented as AIG. Please verify whiteboxes are synthesisable.\n");
holes_module->design->selection_stack.pop_back(); Pass::call(holes_module->design, "clean -purge");
std::stringstream a_buffer; std::stringstream a_buffer;
XAigerWriter writer(holes_module, false /*zinit_mode*/, true /* holes_mode */); XAigerWriter writer(holes_module, false /*zinit_mode*/, true /* holes_mode */);
writer.write_aiger(a_buffer, false /*ascii_mode*/); writer.write_aiger(a_buffer, false /*ascii_mode*/);
holes_module->design->selection_stack.pop_back();
f << "a"; f << "a";
std::string buffer_str = a_buffer.str(); std::string buffer_str = a_buffer.str();
int32_t buffer_size_be = to_big_endian(buffer_str.size()); int32_t buffer_size_be = to_big_endian(buffer_str.size());