riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Make output port a non chain user

This commit is contained in:
Eddie Hung 2019-03-19 13:08:43 -07:00
parent ed32119d13
commit 0ea7eba5f1
1 changed files with 4 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
passes/techmap/shregmap.cc
View File

@ -118,7 +118,7 @@ struct ShregmapTechXilinx7 : ShregmapTech
auto it = sigbit_to_shiftx_offset.find(bit); auto it = sigbit_to_shiftx_offset.find(bit);
if (it == sigbit_to_shiftx_offset.end()) if (it == sigbit_to_shiftx_offset.end())
return; return;
if (cell->type == "$shiftx" && port == "\\A") if (cell && cell->type == "$shiftx" && port == "\\A")
return; return;
sigbit_to_shiftx_offset.erase(it); sigbit_to_shiftx_offset.erase(it);
} }
@ -228,8 +228,10 @@ struct ShregmapWorker
for (auto wire : module->wires()) for (auto wire : module->wires())
{ {
if (wire->port_output || wire->get_bool_attribute("\\keep")) { if (wire->port_output || wire->get_bool_attribute("\\keep")) {
for (auto bit : sigmap(wire)) for (auto bit : sigmap(wire)) {
sigbit_with_non_chain_users.insert(bit); sigbit_with_non_chain_users.insert(bit);
if (opts.tech) opts.tech->non_chain_user(bit, nullptr, {});
}
} }
if (wire->attributes.count("\\init")) { if (wire->attributes.count("\\init")) {