mirror of https://github.com/YosysHQ/yosys.git
read_liberty: s/busses/buses/
This commit is contained in:
parent
56a9202a97
commit
0d5c412807
|
@ -462,7 +462,7 @@ struct LibertyFrontend : public Frontend {
|
||||||
log(" -ignore_miss_data_latch\n");
|
log(" -ignore_miss_data_latch\n");
|
||||||
log(" ignore latches with missing data and/or enable pins\n");
|
log(" ignore latches with missing data and/or enable pins\n");
|
||||||
log("\n");
|
log("\n");
|
||||||
log(" -ignore_busses\n");
|
log(" -ignore_buses\n");
|
||||||
log(" ignore cells with bus interfaces (wide ports)\n");
|
log(" ignore cells with bus interfaces (wide ports)\n");
|
||||||
log("\n");
|
log("\n");
|
||||||
log(" -setattr <attribute_name>\n");
|
log(" -setattr <attribute_name>\n");
|
||||||
|
@ -481,7 +481,7 @@ struct LibertyFrontend : public Frontend {
|
||||||
bool flag_ignore_miss_func = false;
|
bool flag_ignore_miss_func = false;
|
||||||
bool flag_ignore_miss_dir = false;
|
bool flag_ignore_miss_dir = false;
|
||||||
bool flag_ignore_miss_data_latch = false;
|
bool flag_ignore_miss_data_latch = false;
|
||||||
bool flag_ignore_busses = false;
|
bool flag_ignore_buses = false;
|
||||||
bool flag_unit_delay = false;
|
bool flag_unit_delay = false;
|
||||||
std::vector<std::string> attributes;
|
std::vector<std::string> attributes;
|
||||||
|
|
||||||
|
@ -518,8 +518,8 @@ struct LibertyFrontend : public Frontend {
|
||||||
flag_ignore_miss_data_latch = true;
|
flag_ignore_miss_data_latch = true;
|
||||||
continue;
|
continue;
|
||||||
}
|
}
|
||||||
if (arg == "-ignore_busses") {
|
if (arg == "-ignore_buses") {
|
||||||
flag_ignore_busses = true;
|
flag_ignore_buses = true;
|
||||||
continue;
|
continue;
|
||||||
}
|
}
|
||||||
if (arg == "-setattr" && argidx+1 < args.size()) {
|
if (arg == "-setattr" && argidx+1 < args.size()) {
|
||||||
|
@ -593,7 +593,7 @@ struct LibertyFrontend : public Frontend {
|
||||||
|
|
||||||
if (node->id == "bus" && node->args.size() == 1)
|
if (node->id == "bus" && node->args.size() == 1)
|
||||||
{
|
{
|
||||||
if (flag_ignore_busses) {
|
if (flag_ignore_buses) {
|
||||||
log("Ignoring cell %s with a bus interface %s.\n", log_id(module->name), node->args.at(0).c_str());
|
log("Ignoring cell %s with a bus interface %s.\n", log_id(module->name), node->args.at(0).c_str());
|
||||||
delete module;
|
delete module;
|
||||||
goto skip_cell;
|
goto skip_cell;
|
||||||
|
|
|
@ -1,11 +1,11 @@
|
||||||
# Test memory macro gets ignored due to -ignore_busses
|
# Test memory macro gets ignored due to -ignore_buses
|
||||||
read_verilog -noblackbox <<EOF
|
read_verilog -noblackbox <<EOF
|
||||||
module RM_IHPSG13_1P_64x64_c2_bm_bist();
|
module RM_IHPSG13_1P_64x64_c2_bm_bist();
|
||||||
endmodule
|
endmodule
|
||||||
EOF
|
EOF
|
||||||
read_liberty -lib -ignore_busses foundry_data/RM_IHPSG13_1P_64x64_c2_bm_bist_typ_1p20V_25C.lib.filtered.gz
|
read_liberty -lib -ignore_buses foundry_data/RM_IHPSG13_1P_64x64_c2_bm_bist_typ_1p20V_25C.lib.filtered.gz
|
||||||
|
|
||||||
# Test memory macro doesn't get ignored without -ignore_busses
|
# Test memory macro doesn't get ignored without -ignore_buses
|
||||||
# and check the area and capacitance attributes are populated
|
# and check the area and capacitance attributes are populated
|
||||||
design -reset
|
design -reset
|
||||||
read_liberty -lib foundry_data/RM_IHPSG13_1P_64x64_c2_bm_bist_typ_1p20V_25C.lib.filtered.gz
|
read_liberty -lib foundry_data/RM_IHPSG13_1P_64x64_c2_bm_bist_typ_1p20V_25C.lib.filtered.gz
|
||||||
|
|
Loading…
Reference in New Issue