From 0d5c4128072cac0d9635dbc872830fd9e61d101a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Povi=C5=A1er?= <povik@cutebit.org>
Date: Tue, 12 Nov 2024 13:33:41 +0100
Subject: [PATCH] read_liberty: s/busses/buses/

---
 frontends/liberty/liberty.cc  | 10 +++++-----
 tests/liberty/options_test.ys |  6 +++---
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc
index 05d6e5b44..91d390131 100644
--- a/frontends/liberty/liberty.cc
+++ b/frontends/liberty/liberty.cc
@@ -462,7 +462,7 @@ struct LibertyFrontend : public Frontend {
 		log("    -ignore_miss_data_latch\n");
 		log("        ignore latches with missing data and/or enable pins\n");
 		log("\n");
-		log("    -ignore_busses\n");
+		log("    -ignore_buses\n");
 		log("        ignore cells with bus interfaces (wide ports)\n");
 		log("\n");
 		log("    -setattr <attribute_name>\n");
@@ -481,7 +481,7 @@ struct LibertyFrontend : public Frontend {
 		bool flag_ignore_miss_func = false;
 		bool flag_ignore_miss_dir  = false;
 		bool flag_ignore_miss_data_latch = false;
-		bool flag_ignore_busses = false;
+		bool flag_ignore_buses = false;
 		bool flag_unit_delay = false;
 		std::vector<std::string> attributes;
 
@@ -518,8 +518,8 @@ struct LibertyFrontend : public Frontend {
 				flag_ignore_miss_data_latch = true;
 				continue;
 			}
-			if (arg == "-ignore_busses") {
-				flag_ignore_busses = true;
+			if (arg == "-ignore_buses") {
+				flag_ignore_buses = true;
 				continue;
 			}
 			if (arg == "-setattr" && argidx+1 < args.size()) {
@@ -593,7 +593,7 @@ struct LibertyFrontend : public Frontend {
 
 				if (node->id == "bus" && node->args.size() == 1)
 				{
-					if (flag_ignore_busses) {
+					if (flag_ignore_buses) {
 						log("Ignoring cell %s with a bus interface %s.\n", log_id(module->name), node->args.at(0).c_str());
 						delete module;
 						goto skip_cell;
diff --git a/tests/liberty/options_test.ys b/tests/liberty/options_test.ys
index ef6d51353..54957950e 100644
--- a/tests/liberty/options_test.ys
+++ b/tests/liberty/options_test.ys
@@ -1,11 +1,11 @@
-# Test memory macro gets ignored due to -ignore_busses
+# Test memory macro gets ignored due to -ignore_buses
 read_verilog -noblackbox <<EOF
 module RM_IHPSG13_1P_64x64_c2_bm_bist();
 endmodule
 EOF
-read_liberty -lib -ignore_busses foundry_data/RM_IHPSG13_1P_64x64_c2_bm_bist_typ_1p20V_25C.lib.filtered.gz
+read_liberty -lib -ignore_buses foundry_data/RM_IHPSG13_1P_64x64_c2_bm_bist_typ_1p20V_25C.lib.filtered.gz
 
-# Test memory macro doesn't get ignored without -ignore_busses
+# Test memory macro doesn't get ignored without -ignore_buses
 # and check the area and capacitance attributes are populated
 design -reset
 read_liberty -lib foundry_data/RM_IHPSG13_1P_64x64_c2_bm_bist_typ_1p20V_25C.lib.filtered.gz