mirror of https://github.com/YosysHQ/yosys.git
Use mfp<> in equiv_mark
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@ -42,31 +42,7 @@ struct EquivMarkWorker
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int next_region;
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// merge-find
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dict<int, int> region_mf;
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int region_find(int r)
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{
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vector<int> backlog;
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while (region_mf.count(r)) {
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backlog.push_back(r);
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r = region_mf.at(r);
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}
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for (int q : backlog)
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region_mf[q] = r;
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return r;
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}
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void region_merge(int r, int q)
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{
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r = region_find(r);
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q = region_find(q);
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if (r != q)
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region_mf[r] = q;
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}
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mfp<int> region_mf;
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EquivMarkWorker(Module *module) : module(module), sigmap(module)
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{
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@ -116,7 +92,7 @@ struct EquivMarkWorker
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if (cell_regions.count(cell)) {
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if (cell_regions.at(cell) != 0)
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region_merge(cell_regions.at(cell), next_region);
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region_mf.merge(cell_regions.at(cell), next_region);
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continue;
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}
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@ -190,7 +166,7 @@ struct EquivMarkWorker
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dict<int, int> region_wire_count;
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for (int i = 0; i < next_region; i++) {
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int r = region_find(i);
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int r = region_mf.find(i);
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if (final_region_map.count(r) == 0)
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final_region_map[r] = next_final_region++;
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final_region_map[i] = final_region_map[r];
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@ -211,7 +187,7 @@ struct EquivMarkWorker
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pool<int> regions;
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for (auto bit : sigmap(wire))
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if (bit_regions.count(bit))
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regions.insert(region_find(bit_regions.at(bit)));
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regions.insert(region_mf.find(bit_regions.at(bit)));
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if (GetSize(regions) == 1) {
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int r = final_region_map.at(*regions.begin());
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