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docs: RD_DATA is an output, not input

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Charlotte 2023-06-21 17:21:04 +10:00
parent 104edb4587
commit 0c0171bd60
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docs/source/CHAPTER_CellLib.rst
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@ -571,7 +571,7 @@ The ``$mem_v2`` cell has the following ports:
signals for the read ports.
``\RD_DATA``
This input is ``\RD_PORTS*\WIDTH`` bits wide, containing all data
This output is ``\RD_PORTS*\WIDTH`` bits wide, containing all data
signals for the read ports.
``\RD_ARST``