From 0c0171bd6040e44b7013ffca830cfc891db536e6 Mon Sep 17 00:00:00 2001 From: Charlotte Date: Wed, 21 Jun 2023 17:21:04 +1000 Subject: [PATCH] docs: RD_DATA is an output, not input --- docs/source/CHAPTER_CellLib.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/source/CHAPTER_CellLib.rst b/docs/source/CHAPTER_CellLib.rst index c5db434a6..c89040868 100644 --- a/docs/source/CHAPTER_CellLib.rst +++ b/docs/source/CHAPTER_CellLib.rst @@ -571,7 +571,7 @@ The ``$mem_v2`` cell has the following ports: signals for the read ports. ``\RD_DATA`` - This input is ``\RD_PORTS*\WIDTH`` bits wide, containing all data + This output is ``\RD_PORTS*\WIDTH`` bits wide, containing all data signals for the read ports. ``\RD_ARST``