mirror of https://github.com/YosysHQ/yosys.git
select: Add new `t:@<name>` syntax
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@ -876,9 +876,20 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp
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sel.selected_members[mod->name].insert(cell->name);
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} else
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if (arg_memb.compare(0, 2, "t:") == 0) {
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for (auto cell : mod->cells())
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if (match_ids(cell->type, arg_memb.substr(2)))
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sel.selected_members[mod->name].insert(cell->name);
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if (arg_memb.compare(2, 1, "@") == 0) {
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std::string set_name = RTLIL::escape_id(arg_memb.substr(3));
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if (!design->selection_vars.count(set_name))
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log_cmd_error("Selection @%s is not defined!\n", RTLIL::unescape_id(set_name).c_str());
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auto &muster = design->selection_vars[set_name];
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for (auto cell : mod->cells())
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if (muster.selected_modules.count(cell->type))
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sel.selected_members[mod->name].insert(cell->name);
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} else {
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for (auto cell : mod->cells())
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if (match_ids(cell->type, arg_memb.substr(2)))
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sel.selected_members[mod->name].insert(cell->name);
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}
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} else
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if (arg_memb.compare(0, 2, "p:") == 0) {
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for (auto &it : mod->processes)
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@ -1164,6 +1175,9 @@ struct SelectPass : public Pass {
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log(" t:<pattern>\n");
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log(" all cells with a type matching the given pattern\n");
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log("\n");
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log(" t:@<name>\n");
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log(" all cells with a type matching a module in the saved selection <name>\n");
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log("\n");
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log(" p:<pattern>\n");
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log(" all processes with a name matching the given pattern\n");
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log("\n");
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