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memory_libmap: update search order for attributes

This commit is contained in:
N. Engelhardt 2023-10-24 13:55:45 +02:00
parent 833b67af80
commit 080da693d1
1 changed files with 21 additions and 12 deletions
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33
passes/memory/memory_libmap.cc
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@ -482,31 +482,40 @@ void MemMapping::dump_config(MemConfig &cfg) {
} }
std::pair<bool, Const> search_for_attribute(Mem mem, IdString attr) { std::pair<bool, Const> search_for_attribute(Mem mem, IdString attr) {
// priority of attributes:
// 1. attributes on memory itself
// 2. attributes on a read or write port
// 3. attributes on data signal of a read or write port
// 4. attributes on address signal of a read or write port
if (mem.has_attribute(attr)) if (mem.has_attribute(attr))
return std::make_pair(true, mem.attributes.at(attr)); return std::make_pair(true, mem.attributes.at(attr));
for (auto &port: mem.rd_ports){
for (auto &port: mem.rd_ports)
if (port.has_attribute(attr)) if (port.has_attribute(attr))
return std::make_pair(true, port.attributes.at(attr)); return std::make_pair(true, port.attributes.at(attr));
log_debug("looking for attribute %s on signal %s\n", log_id(attr), log_signal(port.data)); for (auto &port: mem.wr_ports)
if (port.has_attribute(attr))
return std::make_pair(true, port.attributes.at(attr));
for (auto &port: mem.rd_ports)
for (SigBit bit: port.data) for (SigBit bit: port.data)
if (bit.is_wire() && bit.wire->has_attribute(attr)) if (bit.is_wire() && bit.wire->has_attribute(attr))
return std::make_pair(true, bit.wire->attributes.at(attr)); return std::make_pair(true, bit.wire->attributes.at(attr));
log_debug("looking for attribute %s on signal %s\n", log_id(attr), log_signal(port.data)); for (auto &port: mem.wr_ports)
for (SigBit bit: port.addr)
if (bit.is_wire() && bit.wire->has_attribute(attr))
return std::make_pair(true, bit.wire->attributes.at(attr));
}
for (auto &port: mem.wr_ports){
if (port.has_attribute(attr))
return std::make_pair(true, port.attributes.at(attr));
log_debug("looking for attribute %s on signal %s\n", log_id(attr), log_signal(port.data));
for (SigBit bit: port.data) for (SigBit bit: port.data)
if (bit.is_wire() && bit.wire->has_attribute(attr)) if (bit.is_wire() && bit.wire->has_attribute(attr))
return std::make_pair(true, bit.wire->attributes.at(attr)); return std::make_pair(true, bit.wire->attributes.at(attr));
for (auto &port: mem.rd_ports)
for (SigBit bit: port.addr) for (SigBit bit: port.addr)
if (bit.is_wire() && bit.wire->has_attribute(attr)) if (bit.is_wire() && bit.wire->has_attribute(attr))
return std::make_pair(true, bit.wire->attributes.at(attr)); return std::make_pair(true, bit.wire->attributes.at(attr));
} for (auto &port: mem.wr_ports)
for (SigBit bit: port.addr)
if (bit.is_wire() && bit.wire->has_attribute(attr))
return std::make_pair(true, bit.wire->attributes.at(attr));
return std::make_pair(false, Const()); return std::make_pair(false, Const());
} }