mirror of https://github.com/YosysHQ/yosys.git
Merge remote-tracking branch 'origin/eddie/fix_carry_wrapper' into xaig_arrival
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commit
070f3ac561
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@ -153,7 +153,7 @@ module \$__ICE40_CARRY_WRAPPER (
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input A, B,
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input A, B,
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(* abc_carry *)
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(* abc_carry *)
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input CI,
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input CI,
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input I0, I3,
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input I0, I3
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);
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);
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parameter LUT = 0;
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parameter LUT = 0;
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SB_CARRY carry (
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SB_CARRY carry (
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@ -83,6 +83,53 @@ static void run_ice40_opts(Module *module)
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}
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}
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continue;
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continue;
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}
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}
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if (cell->type == "$__ICE40_CARRY_WRAPPER")
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{
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SigSpec non_const_inputs, replacement_output;
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int count_zeros = 0, count_ones = 0;
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SigBit inbit[3] = {
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cell->getPort("\\A"),
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cell->getPort("\\B"),
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cell->getPort("\\CI")
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};
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for (int i = 0; i < 3; i++)
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if (inbit[i].wire == nullptr) {
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if (inbit[i] == State::S1)
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count_ones++;
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else
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count_zeros++;
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} else
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non_const_inputs.append(inbit[i]);
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if (count_zeros >= 2)
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replacement_output = State::S0;
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else if (count_ones >= 2)
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replacement_output = State::S1;
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else if (GetSize(non_const_inputs) == 1)
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replacement_output = non_const_inputs;
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if (GetSize(replacement_output)) {
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optimized_co.insert(sigmap(cell->getPort("\\CO")[0]));
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module->connect(cell->getPort("\\CO")[0], replacement_output);
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module->design->scratchpad_set_bool("opt.did_something", true);
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log("Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
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log_id(module), log_id(cell), log_signal(replacement_output));
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cell->type = "$lut";
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cell->setPort("\\A", { cell->getPort("\\I0"), inbit[0], inbit[1], cell->getPort("\\I3") });
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cell->setPort("\\Y", cell->getPort("\\O"));
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cell->unsetPort("\\B");
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cell->unsetPort("\\CI");
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cell->unsetPort("\\I0");
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cell->unsetPort("\\I3");
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cell->unsetPort("\\CO");
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cell->unsetPort("\\O");
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cell->setParam("\\LUT", RTLIL::Const::from_string("0110100110010110"));
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cell->setParam("\\WIDTH", 4);
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}
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continue;
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}
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}
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}
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for (auto cell : sb_lut_cells)
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for (auto cell : sb_lut_cells)
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