riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Fix gcc warning of potentially uninitialised

This commit is contained in:
Eddie Hung 2019-06-20 21:53:27 -07:00
parent b810bf26ab
commit 06bf2ea562
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
passes/techmap/abc9.cc
View File

@ -522,7 +522,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
for (auto c : mapped_mod->cells()) for (auto c : mapped_mod->cells())
{ {
if (c->type == "$_NOT_") { if (c->type == "$_NOT_") {
RTLIL::Cell *cell; RTLIL::Cell *cell = nullptr;
RTLIL::SigBit a_bit = c->getPort("\\A").as_bit(); RTLIL::SigBit a_bit = c->getPort("\\A").as_bit();
RTLIL::SigBit y_bit = c->getPort("\\Y").as_bit(); RTLIL::SigBit y_bit = c->getPort("\\Y").as_bit();
if (!a_bit.wire) { if (!a_bit.wire) {
@ -576,7 +576,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
cell->setPort("\\Y", RTLIL::SigBit(module->wires_[remap_name(y_bit.wire->name)], y_bit.offset)); cell->setPort("\\Y", RTLIL::SigBit(module->wires_[remap_name(y_bit.wire->name)], y_bit.offset));
cell_stats[RTLIL::unescape_id(c->type)]++; cell_stats[RTLIL::unescape_id(c->type)]++;
} }
if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx; if (cell && markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
continue; continue;
} }
cell_stats[RTLIL::unescape_id(c->type)]++; cell_stats[RTLIL::unescape_id(c->type)]++;