mirror of https://github.com/YosysHQ/yosys.git
write_xaiger to flatten 1'bx/1'bz to 1'b0 again
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@ -104,8 +104,10 @@ struct XAigerWriter
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aig_map[bit] = bit2aig(alias_map.at(bit));
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}
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if (bit == State::Sx || bit == State::Sz)
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log_error("Design contains 'x' or 'z' bits. Use 'setundef' to replace those constants.\n");
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if (bit == State::Sx || bit == State::Sz) {
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log_debug("Bit '%s' contains 'x' or 'z' bits. Treating as 1'b0.\n", log_signal(bit));
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aig_map[bit] = 0;
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}
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}
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log_assert(aig_map.at(bit) >= 0);
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