mirror of https://github.com/YosysHQ/yosys.git
Fix gcc warning of potentially uninitialised
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b810bf26ab
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06bf2ea562
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@ -522,7 +522,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
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for (auto c : mapped_mod->cells())
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{
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if (c->type == "$_NOT_") {
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RTLIL::Cell *cell;
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RTLIL::Cell *cell = nullptr;
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RTLIL::SigBit a_bit = c->getPort("\\A").as_bit();
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RTLIL::SigBit y_bit = c->getPort("\\Y").as_bit();
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if (!a_bit.wire) {
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@ -576,7 +576,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
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cell->setPort("\\Y", RTLIL::SigBit(module->wires_[remap_name(y_bit.wire->name)], y_bit.offset));
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cell_stats[RTLIL::unescape_id(c->type)]++;
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}
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if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
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if (cell && markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
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continue;
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}
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cell_stats[RTLIL::unescape_id(c->type)]++;
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