mirror of https://github.com/YosysHQ/yosys.git
Progress in bram testbench
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03b3c02540
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@ -3,34 +3,35 @@
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from __future__ import division
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from __future__ import division
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from __future__ import print_function
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from __future__ import print_function
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import os
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import sys
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import sys
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import random
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import random
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debug_mode = False
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debug_mode = False
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seed = os.getpid()
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def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2):
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def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2):
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while True:
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while True:
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init = random.randrange(2)
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init = random.randrange(2)
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abits = random.randrange(1, 8)
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abits = random.randrange(1, 8)
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dbits = random.randrange(1, 8)
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dbits = random.randrange(1, 8)
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groups = random.randrange(1, 5)
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groups = random.randrange(2, 5)
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if random.randrange(2):
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if random.randrange(2):
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abits = 2 ** random.randrange(1, 4)
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abits = 2 ** random.randrange(1, 4)
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if random.randrange(2):
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if random.randrange(2):
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dbits = 2 ** random.randrange(1, 4)
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dbits = 2 ** random.randrange(1, 4)
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ports = [ random.randrange(3) for i in range(groups) ]
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ports = [ random.randrange(1, 3) for i in range(groups) ]
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wrmode = [ random.randrange(2) for i in range(groups) ]
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wrmode = [ random.randrange(0, 2) for i in range(groups) ]
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enable = [ random.randrange(4) for i in range(groups) ]
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enable = [ random.randrange(0, 4) for i in range(groups) ]
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transp = [ random.randrange(4) for i in range(groups) ]
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transp = [ random.randrange(0, 4) for i in range(groups) ]
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clocks = [ random.randrange(4) for i in range(groups) ]
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clocks = [ random.randrange(1, 4) for i in range(groups) ]
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clkpol = [ random.randrange(4) for i in range(groups) ]
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clkpol = [ random.randrange(0, 4) for i in range(groups) ]
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# XXX
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# XXX
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init = 0
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init = 0
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transp = [ 0 for i in range(groups) ]
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transp = [ 0 for i in range(groups) ]
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clocks = [ 1 for i in range(groups) ]
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clkpol = [ 1 for i in range(groups) ]
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clkpol = [ 1 for i in range(groups) ]
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for p1 in range(groups):
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for p1 in range(groups):
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@ -42,8 +43,9 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2):
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enable[p1] //= 2
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enable[p1] //= 2
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config_ok = True
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config_ok = True
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if wrmode.count(1) <= ports.count(0): config_ok = False
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if sum(ports) > 3: config_ok = False # XXX
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if wrmode.count(0) <= ports.count(0): config_ok = False
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if wrmode.count(1) == 0: config_ok = False
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if wrmode.count(0) == 0: config_ok = False
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if config_ok: break
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if config_ok: break
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print("bram bram_%02d_%02d" % (k1, k2), file=dsc_f)
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print("bram bram_%02d_%02d" % (k1, k2), file=dsc_f)
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@ -82,9 +84,12 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2):
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v_stmts.append("(* nomem2reg *) reg [%d:0] memory [0:%d];" % (dbits-1, 2**abits-1))
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v_stmts.append("(* nomem2reg *) reg [%d:0] memory [0:%d];" % (dbits-1, 2**abits-1))
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portindex = 0
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for p1 in range(groups):
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for p1 in range(groups):
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for p2 in range(ports[p1]):
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for p2 in range(ports[p1]):
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pf = "%c%d" % (chr(ord("A") + p1), p2 + 1)
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pf = "%c%d" % (chr(ord("A") + p1), p2 + 1)
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portindex += 1
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if clocks[p1] and not ("CLK%d" % clocks[p1]) in v_ports:
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if clocks[p1] and not ("CLK%d" % clocks[p1]) in v_ports:
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v_ports.add("CLK%d" % clocks[p1])
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v_ports.add("CLK%d" % clocks[p1])
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@ -133,6 +138,8 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2):
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if not always_hdr in v_always:
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if not always_hdr in v_always:
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v_always[always_hdr] = [list(), list(), list()]
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v_always[always_hdr] = [list(), list(), list()]
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v_always[always_hdr][1].append("`delay(%d)" % portindex);
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v_always[always_hdr][2].append("`delay(%d)" % (sum(ports)-portindex+1));
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if wrmode[p1]:
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if wrmode[p1]:
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for i in range(enable[p1]):
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for i in range(enable[p1]):
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@ -195,7 +202,7 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2):
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print(" %s = %d;" % (p, v), file=tb_f)
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print(" %s = %d;" % (p, v), file=tb_f)
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print(" #1000;", file=tb_f)
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print(" #1000;", file=tb_f)
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for i in range(100):
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for i in range(20 if debug_mode else 100):
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if len(tb_clocks):
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if len(tb_clocks):
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c = random.choice(tb_clocks)
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c = random.choice(tb_clocks)
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print(" %s = !%s;" % (c, c), file=tb_f)
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print(" %s = !%s;" % (c, c), file=tb_f)
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@ -211,6 +218,9 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2):
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print(" end", file=tb_f)
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print(" end", file=tb_f)
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print("endmodule", file=tb_f)
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print("endmodule", file=tb_f)
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print("Rng seed: %d" % seed)
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random.seed(seed)
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for k1 in range(5):
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for k1 in range(5):
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dsc_f = file("temp/brams_%02d.txt" % k1, "w");
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dsc_f = file("temp/brams_%02d.txt" % k1, "w");
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sim_f = file("temp/brams_%02d.v" % k1, "w");
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sim_f = file("temp/brams_%02d.v" % k1, "w");
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@ -220,6 +230,13 @@ for k1 in range(5):
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for f in [sim_f, ref_f, tb_f]:
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for f in [sim_f, ref_f, tb_f]:
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print("`timescale 1 ns / 1 ns", file=f)
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print("`timescale 1 ns / 1 ns", file=f)
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for f in [sim_f, ref_f]:
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print("`ifdef SYNTHESIS", file=f)
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print(" `define delay(n)", file=f)
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print("`else", file=f)
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print(" `define delay(n) #n;", file=f)
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print("`endif", file=f)
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for k2 in range(1 if debug_mode else 10):
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for k2 in range(1 if debug_mode else 10):
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create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2)
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create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2)
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