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Merge branch 'eddie/fix_retime' into xc7srl

This commit is contained in:
Eddie Hung 2019-04-05 15:46:18 -07:00
parent 544843da71 9758701574
commit 0364a5d811
11 changed files with 85 additions and 14 deletions
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10
frontends/ilang/ilang_frontend.cc
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@ -47,16 +47,20 @@ struct IlangFrontend : public Frontend {
log(" -nooverwrite\n");
log(" ignore re-definitions of modules. (the default behavior is to\n");
log(" create an error message if the existing module is not a blackbox\n");
log(" module, and overwrite the existing module if it is a blackbox module.)\n");
log(" module, and overwrite the existing module if it is a blackbox module.)\n");
log("\n");
log(" -overwrite\n");
log(" overwrite existing modules with the same name\n");
log("\n");
log(" -lib\n");
log(" only create empty blackbox modules\n");
log("\n");
}
void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
ILANG_FRONTEND::flag_nooverwrite = false;
ILANG_FRONTEND::flag_overwrite = false;
ILANG_FRONTEND::flag_lib = false;
log_header(design, "Executing ILANG frontend.\n");
@ -73,6 +77,10 @@ struct IlangFrontend : public Frontend {
ILANG_FRONTEND::flag_overwrite = true;
continue;
}
if (arg == "-lib") {
ILANG_FRONTEND::flag_lib = true;
continue;
}
break;
}
extra_args(f, filename, args, argidx);

1
frontends/ilang/ilang_frontend.h
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@ -34,6 +34,7 @@ namespace ILANG_FRONTEND {
extern RTLIL::Design *current_design;
extern bool flag_nooverwrite;
extern bool flag_overwrite;
extern bool flag_lib;
}
YOSYS_NAMESPACE_END

6
frontends/ilang/ilang_parser.y
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@ -37,7 +37,7 @@ namespace ILANG_FRONTEND {
std::vector<std::vector<RTLIL::SwitchRule*>*> switch_stack;
std::vector<RTLIL::CaseRule*> case_stack;
dict<RTLIL::IdString, RTLIL::Const> attrbuf;
bool flag_nooverwrite, flag_overwrite;
bool flag_nooverwrite, flag_overwrite, flag_lib;
bool delete_current_module;
}
using namespace ILANG_FRONTEND;
@ -98,7 +98,7 @@ module:
delete_current_module = false;
if (current_design->has($2)) {
RTLIL::Module *existing_mod = current_design->module($2);
if (!flag_overwrite && attrbuf.count("\\blackbox") && attrbuf.at("\\blackbox").as_bool()) {
if (!flag_overwrite && (flag_lib || (attrbuf.count("\\blackbox") && attrbuf.at("\\blackbox").as_bool()))) {
log("Ignoring blackbox re-definition of module %s.\n", $2);
delete_current_module = true;
} else if (!flag_nooverwrite && !flag_overwrite && !existing_mod->get_bool_attribute("\\blackbox")) {
@ -124,6 +124,8 @@ module:
current_module->fixup_ports();
if (delete_current_module)
delete current_module;
else if (flag_lib)
current_module->makeblackbox();
current_module = nullptr;
} EOL;

24
kernel/rtlil.cc
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@ -641,6 +641,30 @@ RTLIL::Module::~Module()
delete it->second;
}
void RTLIL::Module::makeblackbox()
{
pool<RTLIL::Wire*> delwires;
for (auto it = wires_.begin(); it != wires_.end(); ++it)
if (!it->second->port_input && !it->second->port_output)
delwires.insert(it->second);
for (auto it = memories.begin(); it != memories.end(); ++it)
delete it->second;
memories.clear();
for (auto it = cells_.begin(); it != cells_.end(); ++it)
delete it->second;
cells_.clear();
for (auto it = processes.begin(); it != processes.end(); ++it)
delete it->second;
processes.clear();
remove(delwires);
set_bool_attribute("\\blackbox");
}
void RTLIL::Module::reprocess_module(RTLIL::Design *, dict<RTLIL::IdString, RTLIL::Module *>)
{
log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name));

1
kernel/rtlil.h
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@ -976,6 +976,7 @@ public:
virtual void sort();
virtual void check();
virtual void optimize();
virtual void makeblackbox();
void connect(const RTLIL::SigSig &conn);
void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs);

32
passes/sat/mutate.cc
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@ -934,6 +934,32 @@ struct MutatePass : public Pass {
return;
}
if (opts.module.empty())
log_cmd_error("Missing -module argument.\n");
Module *module = design->module(opts.module);
if (module == nullptr)
log_cmd_error("Module %s not found.\n", log_id(opts.module));
if (opts.cell.empty())
log_cmd_error("Missing -cell argument.\n");
Cell *cell = module->cell(opts.cell);
if (cell == nullptr)
log_cmd_error("Cell %s not found in module %s.\n", log_id(opts.cell), log_id(opts.module));
if (opts.port.empty())
log_cmd_error("Missing -port argument.\n");
if (!cell->hasPort(opts.port))
log_cmd_error("Port %s not found on cell %s.%s.\n", log_id(opts.port), log_id(opts.module), log_id(opts.cell));
if (opts.portbit < 0)
log_cmd_error("Missing -portbit argument.\n");
if (GetSize(cell->getPort(opts.port)) <= opts.portbit)
log_cmd_error("Out-of-range -portbit argument for port %s on cell %s.%s.\n", log_id(opts.port), log_id(opts.module), log_id(opts.cell));
if (opts.mode == "inv") {
mutate_inv(design, opts);
return;
@ -944,6 +970,12 @@ struct MutatePass : public Pass {
return;
}
if (opts.ctrlbit < 0)
log_cmd_error("Missing -ctrlbit argument.\n");
if (GetSize(cell->getPort(opts.port)) <= opts.ctrlbit)
log_cmd_error("Out-of-range -ctrlbit argument for port %s on cell %s.%s.\n", log_id(opts.port), log_id(opts.module), log_id(opts.cell));
if (opts.mode == "cnot0" || opts.mode == "cnot1") {
mutate_cnot(design, opts, opts.mode == "cnot1");
return;

2
passes/techmap/abc.cc
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@ -1674,6 +1674,8 @@ struct AbcPass : public Pass {
}
if (arg == "-dff") {
dff_mode = true;
if (delay_target.empty())
delay_target = "-D 1";
continue;
}
if (arg == "-clk" && argidx+1 < args.size()) {

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techlibs/xilinx/.synth_xilinx.cc.swn Normal file
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techlibs/xilinx/.synth_xilinx.cc.swo Normal file
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8
techlibs/xilinx/ff_map.v
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@ -28,14 +28,14 @@ module \$_DFF_P_ (input D, C, output Q); FDRE #(.INIT(|0)) _TECHMAP_REPL
module \$_DFFE_NP_ (input D, C, E, output Q); FDRE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0)); endmodule
module \$_DFFE_PP_ (input D, C, E, output Q); FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0)); endmodule
module \$_DFF_NN0_ (input D, C, R, output Q); FDCE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R)); endmodule
module \$_DFF_NN0_ (input D, C, R, output Q); \$_DFF_NP0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
module \$_DFF_NP0_ (input D, C, R, output Q); FDCE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R)); endmodule
module \$_DFF_PN0_ (input D, C, R, output Q); FDCE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R)); endmodule
module \$_DFF_PN0_ (input D, C, R, output Q); \$_DFF_PP0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
module \$_DFF_PP0_ (input D, C, R, output Q); FDCE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R)); endmodule
module \$_DFF_NN1_ (input D, C, R, output Q); FDPE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R)); endmodule
module \$_DFF_NN1_ (input D, C, R, output Q); \$_DFF_NP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
module \$_DFF_NP1_ (input D, C, R, output Q); FDPE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); endmodule
module \$_DFF_PN1_ (input D, C, R, output Q); FDPE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R)); endmodule
module \$_DFF_PN1_ (input D, C, R, output Q); \$_DFF_PP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
module \$_DFF_PP1_ (input D, C, R, output Q); FDPE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); endmodule
`endif

15
techlibs/xilinx/synth_xilinx.cc
View File

@ -115,7 +115,7 @@ struct SynthXilinxPass : public Pass
log(" opt -full\n");
log(" simplemap t:$dff t:$dffe (without -nosrl and without -retime only)\n");
log(" shregmap -tech xilinx -minlen 3 (without -nosrl and without -retime only)\n");
log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v\n");
log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v\n");
log(" opt -fast\n");
log("\n");
log(" map_cells:\n");
@ -125,10 +125,10 @@ struct SynthXilinxPass : public Pass
log(" clean\n");
log("\n");
log(" map_luts:\n");
log(" abc -luts 2:2,3,6:5,10,20 [-dff] (without '-vpr' only!)\n");
log(" abc -lut 5 [-dff] (with '-vpr' only!)\n");
log(" techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?\n");
log(" abc -luts 2:2,3,6:5,10,20 [-dff]\n");
log(" clean\n");
log(" techmap -map +/xilinx/lut_map.v\n");
log(" techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v");
log("\n");
log(" check:\n");
log(" hierarchy -check\n");
@ -272,9 +272,9 @@ struct SynthXilinxPass : public Pass
}
if (vpr) {
Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v -D _EXPLICIT_CARRY");
Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY");
} else {
Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v");
Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v");
}
Pass::call(design, "hierarchy -check");
@ -291,9 +291,10 @@ struct SynthXilinxPass : public Pass
if (check_label(active, run_from, run_to, "map_luts"))
{
Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?");
Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
Pass::call(design, "clean");
Pass::call(design, "techmap -map +/xilinx/lut_map.v");
Pass::call(design, "techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v");
}
if (check_label(active, run_from, run_to, "check"))