mirror of https://github.com/YosysHQ/yosys.git
abc9_ops: -prep_hier to create unmap module that removes Q's (* init *)
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13f9d65b6f
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02df0198b6
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@ -230,9 +230,12 @@ void prep_hier(RTLIL::Design *design, bool dff_mode)
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auto unmap_module = unmap_design->addModule(derived_type);
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auto unmap_module = unmap_design->addModule(derived_type);
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for (auto port : derived_module->ports) {
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for (auto port : derived_module->ports) {
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auto w = unmap_module->addWire(port, derived_module->wire(port));
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auto w = unmap_module->addWire(port, derived_module->wire(port));
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// Do not propagate (* init *) values inside the box
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// Do not propagate (* init *) values into the box,
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if (w->port_output)
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// in fact, remove it from outside too
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w->attributes.erase(ID::init);
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if (w->port_output && w->attributes.erase(ID::init)) {
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auto r = unmap_module->addWire(stringf("\\_TECHMAP_REMOVEINIT_%s_", log_id(port)));
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unmap_module->connect(r, State::S1);
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}
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}
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}
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unmap_module->ports = derived_module->ports;
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unmap_module->ports = derived_module->ports;
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unmap_module->check();
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unmap_module->check();
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@ -771,7 +774,6 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
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continue;
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continue;
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if (!box_module->get_bool_attribute(ID::abc9_box))
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if (!box_module->get_bool_attribute(ID::abc9_box))
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continue;
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continue;
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log_cell(cell);
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log_assert(cell->parameters.empty());
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log_assert(cell->parameters.empty());
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log_assert(box_module->get_blackbox_attribute());
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log_assert(box_module->get_blackbox_attribute());
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