2019-09-27 14:50:20 -05:00
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read_verilog latches.v
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2019-09-10 00:08:03 -05:00
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design -save read
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2019-09-27 14:50:20 -05:00
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proc
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2019-09-10 00:08:03 -05:00
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async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock
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2019-09-27 14:50:20 -05:00
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flatten
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2019-09-10 00:08:03 -05:00
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equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
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2019-09-27 14:50:20 -05:00
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synth_xilinx
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2019-09-10 00:36:59 -05:00
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flatten
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cd top
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2019-09-27 14:50:20 -05:00
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select -assert-count 1 t:LUT1
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select -assert-count 2 t:LUT3
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2019-09-11 09:01:19 -05:00
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#Xilinx Vivado synthesizes LDCE cell for this case. Need support it.
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2019-09-10 00:08:03 -05:00
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select -assert-count 3 t:$_DLATCH_P_
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2019-09-10 00:36:59 -05:00
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select -assert-none t:LUT1 t:LUT3 t:$_DLATCH_P_ %% t:* %D
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