yosys/tests/opt/opt_rmdff_sat.ys

read_verilog opt_rmdff_sat.v
prep -flatten
opt_dff -sat -nosdff
simplemap
select -assert-count 5 t:$_DFF_P_
Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder" This reverts commit c851dc13108021834533094a8a3236da6d9e0161, reversing changes made to f54bf1631ff37a83733c162e6ebd188c1d5ea18f. 2019-08-12 14:06:45 -05:00			`read_verilog opt_rmdff_sat.v`
Optimizing DFFs whose initial value prevents their value from changing This is a proof of concept implementation that invokes SAT solver via Pass::call method. 2019-05-28 01:48:21 -05:00			`prep -flatten`
Add opt_dff pass. 2020-07-14 17:58:07 -05:00			`opt_dff -sat -nosdff`
			`simplemap`
Refactor "opt_rmdff -sat" Signed-off-by: Clifford Wolf <clifford@clifford.at> 2019-06-20 06:44:21 -05:00			`select -assert-count 5 t:$_DFF_P_`