mirror of https://github.com/YosysHQ/yosys.git
26 lines
463 B
Verilog
26 lines
463 B
Verilog
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// expect-wr-ports 1
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// expect-rd-ports 1
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module test(
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input clk,
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input wr_en1, wr_en2, wr_en3,
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input [3:0] wr_addr1, wr_addr2, wr_addr3,
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input [15:0] wr_data,
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input [3:0] rd_addr,
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output reg [31:0] rd_data
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);
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reg [31:0] mem [0:15];
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always @(posedge clk) begin
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if (wr_en1)
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mem[wr_addr1][15:0] <= wr_data;
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else if (wr_en2)
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mem[wr_addr2][23:8] <= wr_data;
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else if (wr_en3)
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mem[wr_addr3][31:16] <= wr_data;
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rd_data <= mem[rd_addr];
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end
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endmodule
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