mirror of https://github.com/YosysHQ/yosys.git
24 lines
721 B
Verilog
24 lines
721 B
Verilog
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/*
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Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 72].
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*/
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module top (din, write_en, waddr, wclk, raddr, rclk, dout);
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parameter addr_width = 8;
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parameter data_width = 8;
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input [addr_width-1:0] waddr, raddr;
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input [data_width-1:0] din;
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input write_en, wclk, rclk;
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output [data_width-1:0] dout;
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reg [data_width-1:0] dout;
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reg [data_width-1:0] mem [(1<<addr_width)-1:0]
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/* synthesis syn_ramstyle = "no_rw_check" */ ;
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always @(posedge wclk) // Write memory.
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begin
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if (write_en)
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mem[waddr] <= din; // Using write address bus.
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end
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always @(posedge rclk) // Read memory.
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begin
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dout <= mem[raddr]; // Using read address bus.
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end
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endmodule
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