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yosys/techlibs/anlogic/Makefile.inc

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Initial support for Anlogic FPGA
2018-12-01 11:28:54 -06:00
OBJS += techlibs/anlogic/synth_anlogic.o
OBJS += techlibs/anlogic/anlogic_eqn.o
Proper arith for Anlogic and use standard pass
2019-08-12 13:19:54 -05:00
OBJS += techlibs/anlogic/anlogic_fixcarry.o
Initial support for Anlogic FPGA
2018-12-01 11:28:54 -06:00
anlogic: support BRAM mapping Anlogic FPGAs all have two kinds of BRAMs, one is 9bit*1K when being true dual port (or 18bit*512 when simple dual port), the other is 16bit*2K. Supports mapping of these two kinds of BRAMs. 9Kbit BRAM in SDP mode and 32Kbit BRAM with 8bit width are not support yet. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2021-12-17 06:25:32 -06:00
GENFILES += techlibs/anlogic/brams_init_16.vh
GENFILES += techlibs/anlogic/brams_init_9.vh
GENFILES += techlibs/anlogic/brams_init_8.vh
EXTRA_OBJS += techlibs/anlogic/brams_init.mk
.SECONDARY: techlibs/anlogic/brams_init.mk
techlibs/anlogic/brams_init.mk: techlibs/anlogic/brams_init.py
$(Q) mkdir -p techlibs/anlogic
$(P) $(PYTHON_EXECUTABLE) $<
$(Q) touch $@
techlibs/anlogic/brams_init_16.vh: techlibs/anlogic/brams_init.mk
techlibs/anlogic/brams_init_9.vh: techlibs/anlogic/brams_init.mk
techlibs/anlogic/brams_init_8.vh: techlibs/anlogic/brams_init.mk
Initial support for Anlogic FPGA
2018-12-01 11:28:54 -06:00
$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_map.v))
$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/arith_map.v))
$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_sim.v))
anlogic: fix Makefile.inc During the addition of DRAM inferring support, the installation of eagle_bb.v is accidentally removed. Fix this issue. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-18 20:23:58 -06:00
$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/eagle_bb.v))
Harmonize BRAM/LUTRAM descriptions across all of Yosys. This commit: * renames all remaining instances of "DRAM" (which is ambiguous) to "LUTRAM" (which is not), finishing the work started in the commit 698ab9be; * renames memory rule files to brams.txt/lutrams.txt; * adds/renames script labels map_bram/map_lutram; * extracts where necessary script labels map_ffram and map_gates; * adds where necessary options -nobram/-nolutram. The end result is that BRAM/LUTRAM/FFRAM aspects of every target are now consistent with each other. Per architecture: * anlogic: rename drams.txt→lutrams.txt, add -nolutram, add :map_lutram, :map_ffram, :map_gates * ecp5: rename bram.txt→brams.txt, lutram.txt→lutrams.txt * efinix: rename bram.txt→brams.txt, add -nobram, add :map_ffram, :map_gates * gowin: rename bram.txt→brams.txt, dram.txt→lutrams.txt, rename -nodram→-nolutram (-nodram still recognized), rename :bram→:map_bram, :dram→:map_lutram, add :map_ffram, :map_gates
2020-01-01 06:30:00 -06:00
$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/lutrams.txt))
$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/lutrams_map.v))
$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/lutram_init_16x4.vh))
anlogic: support BRAM mapping Anlogic FPGAs all have two kinds of BRAMs, one is 9bit*1K when being true dual port (or 18bit*512 when simple dual port), the other is 16bit*2K. Supports mapping of these two kinds of BRAMs. 9Kbit BRAM in SDP mode and 32Kbit BRAM with 8bit width are not support yet. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2021-12-17 06:25:32 -06:00
$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/brams.txt))
$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/brams_map.v))
$(eval $(call add_gen_share_file,share/anlogic,techlibs/anlogic/brams_init_16.vh))
$(eval $(call add_gen_share_file,share/anlogic,techlibs/anlogic/brams_init_9.vh))
$(eval $(call add_gen_share_file,share/anlogic,techlibs/anlogic/brams_init_8.vh))