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yosys/techlibs/anlogic/Makefile.inc

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Initial support for Anlogic FPGA
2018-12-01 11:28:54 -06:00
OBJS += techlibs/anlogic/synth_anlogic.o
OBJS += techlibs/anlogic/anlogic_eqn.o
Proper arith for Anlogic and use standard pass
2019-08-12 13:19:54 -05:00
OBJS += techlibs/anlogic/anlogic_fixcarry.o
Initial support for Anlogic FPGA
2018-12-01 11:28:54 -06:00
$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_map.v))
$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/arith_map.v))
$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_sim.v))
anlogic: fix Makefile.inc During the addition of DRAM inferring support, the installation of eagle_bb.v is accidentally removed. Fix this issue. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-18 20:23:58 -06:00
$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/eagle_bb.v))
anlogic: add support for Eagle Distributed RAM The MSLICEs on the Eagle series of FPGA can be configured as Distributed RAM. Enable to synthesis to DRAM. As the Anlogic software suite doesn't support any 'bx to exist in the initializtion data of DRAM, do not enable the initialization support of the inferred DRAM. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-14 02:50:37 -06:00
$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/drams.txt))
$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/drams_map.v))
anlogic: implement DRAM initialization As the TD tool doesn't accept the DRAM cell to contain unknown values in the initial value, the initialzation support of DRAM is previously skipped. Now add the support by add a new pass to determine unknown values in the initial value. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-18 20:18:47 -06:00
$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/dram_init_16x4.vh))