mirror of https://github.com/YosysHQ/yosys.git
10 lines
218 B
Verilog
10 lines
218 B
Verilog
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module test(input CLK, ADDR,
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input [7:0] DIN,
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output reg [7:0] DOUT);
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reg [7:0] mem [0:1];
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always @(posedge CLK) begin
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mem[ADDR] <= DIN;
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DOUT <= mem[ADDR];
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end
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endmodule
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