mirror of https://github.com/YosysHQ/yosys.git
23 lines
329 B
Verilog
23 lines
329 B
Verilog
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module dffn(input CLK, D, output reg Q, output QN);
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always @(negedge CLK)
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Q <= D;
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assign QN = ~Q;
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endmodule
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module dffsr(input CLK, D, CLEAR, PRESET, output reg Q, output QN);
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always @(posedge CLK, posedge CLEAR, posedge PRESET)
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if (CLEAR)
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Q <= 0;
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else if (PRESET)
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Q <= 1;
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else
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Q <= D;
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assign QN = ~Q;
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endmodule
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