yosys/tests/techmap/dfflegalize_adlatch.ys

read_verilog -icells <<EOT

module adlatch0(input E, R, D, output [2:0] Q);
$_DLATCH_PP0_ ff0 (.E(E), .R(R), .D(D), .Q(Q[0]));
$_DLATCH_PN0_ ff1 (.E(E), .R(R), .D(D), .Q(Q[1]));
$_DLATCH_NP0_ ff2 (.E(E), .R(R), .D(D), .Q(Q[2]));
endmodule

module adlatch1(input E, R, D, output [2:0] Q);
$_DLATCH_PP1_ ff0 (.E(E), .R(R), .D(D), .Q(Q[0]));
$_DLATCH_PN1_ ff1 (.E(E), .R(R), .D(D), .Q(Q[1]));
$_DLATCH_NP1_ ff2 (.E(E), .R(R), .D(D), .Q(Q[2]));
endmodule

module top(input C, E, R, D, output [5:0] Q);
adlatch0 adlatch0_(.E(E), .R(R), .D(D), .Q(Q[2:0]));
adlatch1 adlatch1_(.E(E), .R(R), .D(D), .Q(Q[5:3]));
endmodule

EOT

design -save orig
flatten
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ x
equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ x


# Convert everything to ADLATCHs.

design -load orig
dfflegalize -cell $_DLATCH_PP0_ x

select -assert-count 2 adlatch0/t:$_NOT_
select -assert-count 8 adlatch1/t:$_NOT_
select -assert-count 0 adlatch0/t:$_MUX_
select -assert-count 0 adlatch1/t:$_MUX_
select -assert-count 6 t:$_DLATCH_PP0_
select -assert-none t:$_DLATCH_PP0_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i


# Convert everything to DLATCHSRs.

design -load orig
dfflegalize -cell $_DLATCHSR_PPP_ x

select -assert-count 2 adlatch0/t:$_NOT_
select -assert-count 2 adlatch1/t:$_NOT_
select -assert-count 0 adlatch0/t:$_MUX_
select -assert-count 0 adlatch1/t:$_MUX_
select -assert-count 6 t:$_DLATCHSR_PPP_
select -assert-none t:$_DLATCHSR_PPP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i